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litex-boards
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platforms/targets: keep in sync with litex.

This commit is contained in:
Florent Kermarrec 2020-07-22 08:53:49 +02:00
parent 0ee4b215b9
commit 19d0b95867
2 changed files with 1 additions and 2 deletions
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1
litex_boards/platforms/nexys4ddr.py
View File

@ -73,6 +73,7 @@ _io = [
Subsignal("data", Pins("C2 E1 F1 D2"), Misc("PULLUP True")), Subsignal("data", Pins("C2 E1 F1 D2"), Misc("PULLUP True")),
Subsignal("cmd", Pins("C1"), Misc("PULLUP True")), Subsignal("cmd", Pins("C1"), Misc("PULLUP True")),
Subsignal("clk", Pins("B1")), Subsignal("clk", Pins("B1")),
Subsignal("cd", Pins("A1")),
Misc("SLEW=FAST"), Misc("SLEW=FAST"),
IOStandard("LVCMOS33"), IOStandard("LVCMOS33"),
), ),

2
litex_boards/targets/nexys_video.py
View File

@ -30,7 +30,6 @@ class _CRG(Module):
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain() self.clock_domains.cd_clk200 = ClockDomain()
self.clock_domains.cd_clk100 = ClockDomain() self.clock_domains.cd_clk100 = ClockDomain()
self.clock_domains.cd_sd = ClockDomain()
# # # # # #
@ -42,7 +41,6 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_clk200, 200e6) pll.create_clkout(self.cd_clk200, 200e6)
pll.create_clkout(self.cd_clk100, 100e6) pll.create_clkout(self.cd_clk100, 100e6)
pll.create_clkout(self.cd_sd, 10e6)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)