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Take Ethernet PHY out of reset so default clock is 125 Mhz (and baud rate is 115,200)

This commit is contained in:
Skip Hansen 2020-05-25 10:11:03 -07:00
parent 9b572ece0e
commit 1ab46562bd
2 changed files with 9 additions and 0 deletions
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3
litex_boards/platforms/pano_logic_g2.py Normal file → Executable file
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@ -97,6 +97,9 @@ _io = [
Subsignal("cke", Pins("D2"), IOStandard("SSTL18_II")), Subsignal("cke", Pins("D2"), IOStandard("SSTL18_II")),
Subsignal("odt", Pins("J6"), IOStandard("SSTL18_II")), Subsignal("odt", Pins("J6"), IOStandard("SSTL18_II")),
), ),
# Ethernet phy reset (clk125 is 25 Mhz instead of 125 Mhz if reset is active)
("gmii_rst_n", 0, Pins("R11"), IOStandard("LVCMOS33")),
] ]
# Platform ----------------------------------------------------------------------------------------- # Platform -----------------------------------------------------------------------------------------

6
litex_boards/targets/pano_logic_g2.py
View File

@ -46,6 +46,12 @@ class BaseSoC(SoCCore):
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)
self.add_csr("leds") self.add_csr("leds")
# Take Ethernet Phy out of reset for SYSCLK of 125 Mhz
gmii_rst_n = platform.request("gmii_rst_n")
self.comb += [
gmii_rst_n.eq(1)
]
# Build -------------------------------------------------------------------------------------------- # Build --------------------------------------------------------------------------------------------
def main(): def main():