decklink_quad_hdmi: Add Clk IOs, use clk200 as primary clk and add JTAGBone.

litex_boards/platforms/decklink_quad_hdmi_recorder.py

@@ -12,15 +12,21 @@ from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
 # IOs ----------------------------------------------------------------------------------------------
 
 _io = [
-    # Clk / Rst (SI5338A).
-
-    # TODO (We'll use the 100MHz PCIe Clock for now).
+    # Clk / Rst.
+    # TODO: Document SI5338A.
+    ("clk24",  0, Pins("P26"),  IOStandard("LVCMOS15")),
+    ("clk200", 0,
+        Subsignal("p", Pins("AJ29"), IOStandard("LVDS")),
+        Subsignal("n", Pins("AK30"), IOStandard("LVDS"))
+    ),
+    ("clk",   0, Pins("AJ29"), IOStandard("LVCMOS15")),
+    ("clk",   0, Pins("AK30"), IOStandard("LVCMOS15")),
 
     # Debug.
-    ("debug", 0, Pins("AL34"), IOStandard("LVCMOS25")),
-    ("debug", 1, Pins("AM34"), IOStandard("LVCMOS25")),
-    ("debug", 2, Pins("AN34"), IOStandard("LVCMOS25")),
-    ("debug", 3, Pins("AP34"), IOStandard("LVCMOS25")),
+    ("debug", 0, Pins("AL34"), IOStandard("LVCMOS15")),
+    ("debug", 1, Pins("AM34"), IOStandard("LVCMOS15")),
+    ("debug", 2, Pins("AN34"), IOStandard("LVCMOS15")),
+    ("debug", 3, Pins("AP34"), IOStandard("LVCMOS15")),
 
     # SPIFlash (MX25L25645GSXDI).
 
@@ -153,6 +159,9 @@ _io = [
 # Platform -----------------------------------------------------------------------------------------
 
 class Platform(XilinxPlatform):
+    default_clk_name   = "clk200"
+    default_clk_period = 1e9/200e6
+
     def __init__(self):
         XilinxPlatform.__init__(self, "xcku040-ffva1156-2-e", _io, toolchain="vivado")
 
@@ -161,3 +170,5 @@ class Platform(XilinxPlatform):
 
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)
+        self.add_period_constraint(self.lookup_request("clk24",  loose=True), 1e9/24e6)
+        self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6)

litex_boards/targets/decklink_quad_hdmi_recorder.py

@@ -19,6 +19,7 @@ from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.builder import *
 
+from litedram.common import PHYPadsReducer
 from litedram.modules import MT41J256M16
 from litedram.phy import usddrphy
 
@@ -37,8 +38,7 @@ class _CRG(Module):
         # # #
 
         self.submodules.pll = pll = USMMCM(speedgrade=-2)
-        self.comb += pll.reset.eq(ResetSignal("pcie"))
-        pll.register_clkin(ClockSignal("pcie"), 250e6)
+        pll.register_clkin(platform.request("clk200"), 200e6)
         pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
         pll.create_clkout(self.cd_idelay, 200e6)
         platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
@@ -54,7 +54,7 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(200e6), with_pcie=False, **kwargs):
+    def __init__(self, sys_clk_freq=int(125e6), with_pcie=False, **kwargs):
         platform = quad_hdmi_recorder.Platform()
 
         # SoCCore ----------------------------------------------------------------------------------
@@ -67,9 +67,13 @@ class BaseSoC(SoCCore):
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
 
+        # JTAGBone  --------------------------------------------------------------------------------
+        self.add_jtagbone()
+
         # DDR3 SDRAM -------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
-            self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"),
+            self.submodules.ddrphy = usddrphy.USDDRPHY(
+                pads             = PHYPadsReducer(platform.request("ddram"), [0]),
                 memtype          = "DDR3",
                 sys_clk_freq     = sys_clk_freq,
                 iodelay_clk_freq = 200e6)
@@ -87,9 +91,9 @@ class BaseSoC(SoCCore):
                 data_width = 128,
                 bar0_size  = 0x20000)
             self.add_pcie(phy=self.pcie_phy, ndmas=1)
-        # False Paths (FIXME: Improve integration).
-        platform.toolchain.pre_placement_commands.append("set_false_path -from [get_clocks sys_clk_1] -to [get_clocks pcie_clk_1]")
-        platform.toolchain.pre_placement_commands.append("set_false_path -from [get_clocks pcie_clk_1] -to [get_clocks sys_clk_1]")
+            # False Paths (FIXME: Improve integration).
+            platform.toolchain.pre_placement_commands.append("set_false_path -from [get_clocks sys_clk_1] -to [get_clocks pcie_clk_1]")
+            platform.toolchain.pre_placement_commands.append("set_false_path -from [get_clocks pcie_clk_1] -to [get_clocks sys_clk_1]")
 
 # Build --------------------------------------------------------------------------------------------
 
@@ -97,7 +101,7 @@ def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Blackmagic Decklink Quad HDMI Recorder")
     parser.add_argument("--build",        action="store_true", help="Build bitstream")
     parser.add_argument("--load",         action="store_true", help="Load bitstream")
-    parser.add_argument("--sys-clk-freq", default=200e6,       help="System clock frequency (default: 200MHz)")
+    parser.add_argument("--sys-clk-freq", default=125e6,       help="System clock frequency (default: 125MHz)")
     parser.add_argument("--with-pcie",    action="store_true", help="Enable PCIe support")
     parser.add_argument("--driver",       action="store_true", help="Generate PCIe driver")
     builder_args(parser)