basys3: Review/Simplify and fix build.
This commit is contained in:
Florent Kermarrec
parent
25867c4dcb
commit
1c4825e7c4
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@ -12,7 +12,7 @@ from litex.build.openocd import OpenOCD
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_io = [
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# Clk / Rst
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("clk100", 0, Pins("W3"), IOStandard("LVCMOS33")),
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("clk100", 0, Pins("W5"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("U16"), IOStandard("LVCMOS33")),
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@ -24,13 +24,13 @@ _io = [
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("user_led", 6, Pins("U14"), IOStandard("LVCMOS33")),
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("user_led", 7, Pins("V14"), IOStandard("LVCMOS33")),
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("user_led", 8, Pins("V13"), IOStandard("LVCMOS33")),
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("user_led", 9, Pins("V3"), IOStandard("LVCMOS33")),
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("user_led", 10, Pins("W3"), IOStandard("LVCMOS33")),
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("user_led", 11, Pins("U3"), IOStandard("LVCMOS33")),
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("user_led", 12, Pins("P3"), IOStandard("LVCMOS33")),
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("user_led", 13, Pins("N3"), IOStandard("LVCMOS33")),
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("user_led", 14, Pins("P1"), IOStandard("LVCMOS33")),
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("user_led", 15, Pins("L1"), IOStandard("LVCMOS33")),
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("user_led", 9, Pins("V3"), IOStandard("LVCMOS33")),
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("user_led", 10, Pins("W3"), IOStandard("LVCMOS33")),
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("user_led", 11, Pins("U3"), IOStandard("LVCMOS33")),
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("user_led", 12, Pins("P3"), IOStandard("LVCMOS33")),
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("user_led", 13, Pins("N3"), IOStandard("LVCMOS33")),
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("user_led", 14, Pins("P1"), IOStandard("LVCMOS33")),
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("user_led", 15, Pins("L1"), IOStandard("LVCMOS33")),
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# Switches
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("user_sw", 0, Pins("V17"), IOStandard("LVCMOS33")),
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@ -43,12 +43,12 @@ _io = [
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("user_sw", 7, Pins("W13"), IOStandard("LVCMOS33")),
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("user_sw", 8, Pins("V2"), IOStandard("LVCMOS33")),
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("user_sw", 9, Pins("T3"), IOStandard("LVCMOS33")),
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("user_sw", 10, Pins("T2"), IOStandard("LVCMOS33")),
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("user_sw", 11, Pins("R3"), IOStandard("LVCMOS33")),
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("user_sw", 10, Pins("T2"), IOStandard("LVCMOS33")),
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("user_sw", 11, Pins("R3"), IOStandard("LVCMOS33")),
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("user_sw", 12, Pins("W2"), IOStandard("LVCMOS33")),
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("user_sw", 13, Pins("U1"), IOStandard("LVCMOS33")),
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("user_sw", 14, Pins("T1"), IOStandard("LVCMOS33")),
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("user_sw", 15, Pins("R2"), IOStandard("LVCMOS33")),
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("user_sw", 13, Pins("U1"), IOStandard("LVCMOS33")),
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("user_sw", 14, Pins("T1"), IOStandard("LVCMOS33")),
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("user_sw", 15, Pins("R2"), IOStandard("LVCMOS33")),
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# Buttons
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("user_btnu", 0, Pins("T18"), IOStandard("LVCMOS33")),
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@ -85,10 +85,10 @@ _io = [
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("pmoda", "J1 L2 J2 G2 H1 K2 H2 G3"),
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("pmodb", "A14 A16 B15 B16 A15 A17 C15 C16"),
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("pmodc", "K17 M18 N17 P18 L17 M19 P17 R18"),
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("pmodxdac", "J3 L3 M2 N2 K3 M3 M1 N1"),
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("pmoda", "J1 L2 J2 G2 H1 K2 H2 G3"),
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("pmodb", "A14 A16 B15 B16 A15 A17 C15 C16"),
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("pmodc", "K17 M18 N17 P18 L17 M19 P17 R18"),
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("pmodxdac", " J3 L3 M2 N2 K3 M3 M1 N1"),
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]
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# PMODS --------------------------------------------------------------------------------------------
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@ -129,4 +129,4 @@ class Platform(XilinxPlatform):
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
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self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
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@ -1,3 +1,5 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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@ -6,7 +8,6 @@
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import os
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import argparse
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from litex.build.xilinx import platform
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from migen import *
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@ -19,38 +20,27 @@ from litex.soc.integration.builder import *
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from litex.soc.cores.video import VideoVGAPHY
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT47H64M16
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from litedram.phy import s7ddrphy
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from liteeth.phy.rmii import LiteEthPHYRMII
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_idelay = ClockDomain()
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self.clock_domains.cd_vga = ClockDomain(reset_less=True)
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self.submodules.pll = pll = S7MMCM(speedgrade=-1)
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self.comb += pll.reset.eq(~platform.request("user_btnc") | self.rst)
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pll.register_clkin(platform.request("clk100"), 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_idelay, 200e6)
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pll.create_clkout(self.cd_vga, 40e6)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin)
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_vga, 40e6)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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#platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk100_IBUF]")
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(75e6), with_video_terminal=False, with_video_framebuffer=False, **kwargs):
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def __init__(self, sys_clk_freq=int(75e6), with_video_terminal=False, **kwargs):
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platform = basys3.Platform()
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# SoCCore ----------------------------------_-----------------------------------------------
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@ -62,13 +52,13 @@ class BaseSoC(SoCCore):
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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if with_video_terminal or with_video_framebuffer:
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# Video ------------------------------------------------------------------------------------
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if with_video_terminal:
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self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga")
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if with_video_terminal:
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self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
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if with_video_framebuffer:
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self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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@ -76,16 +66,15 @@ class BaseSoC(SoCCore):
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Basys3")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default: 75MHz)")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default: 75MHz)")
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sdopts = parser.add_mutually_exclusive_group()
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sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
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sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
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parser.add_argument("--sdcard-adapter", type=str, help="SDCard PMOD adapter: digilent (default) or numato")
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sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
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sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
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parser.add_argument("--sdcard-adapter", type=str, help="SDCard PMOD adapter: digilent (default) or numato")
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viopts = parser.add_mutually_exclusive_group()
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viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA)")
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viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (VGA)")
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viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA)")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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@ -93,7 +82,6 @@ def main():
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_video_terminal = args.with_video_terminal,
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with_video_framebuffer = args.with_video_framebuffer,
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**soc_core_argdict(args)
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)
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soc.platform.add_extension(basys3._sdcard_pmod_io)
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