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basys3: Review/Simplify and fix build.

This commit is contained in:
Florent Kermarrec 2021-05-25 08:44:26 +02:00
parent 25867c4dcb
commit 1c4825e7c4
2 changed files with 36 additions and 48 deletions
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36
litex_boards/platforms/digilent_basys3.py
View File

@ -12,7 +12,7 @@ from litex.build.openocd import OpenOCD
_io = [ _io = [
# Clk / Rst # Clk / Rst
("clk100", 0, Pins("W3"), IOStandard("LVCMOS33")), ("clk100", 0, Pins("W5"), IOStandard("LVCMOS33")),
# Leds # Leds
("user_led", 0, Pins("U16"), IOStandard("LVCMOS33")), ("user_led", 0, Pins("U16"), IOStandard("LVCMOS33")),
@ -24,13 +24,13 @@ _io = [
("user_led", 6, Pins("U14"), IOStandard("LVCMOS33")), ("user_led", 6, Pins("U14"), IOStandard("LVCMOS33")),
("user_led", 7, Pins("V14"), IOStandard("LVCMOS33")), ("user_led", 7, Pins("V14"), IOStandard("LVCMOS33")),
("user_led", 8, Pins("V13"), IOStandard("LVCMOS33")), ("user_led", 8, Pins("V13"), IOStandard("LVCMOS33")),
("user_led", 9, Pins("V3"), IOStandard("LVCMOS33")), ("user_led", 9, Pins("V3"), IOStandard("LVCMOS33")),
("user_led", 10, Pins("W3"), IOStandard("LVCMOS33")), ("user_led", 10, Pins("W3"), IOStandard("LVCMOS33")),
("user_led", 11, Pins("U3"), IOStandard("LVCMOS33")), ("user_led", 11, Pins("U3"), IOStandard("LVCMOS33")),
("user_led", 12, Pins("P3"), IOStandard("LVCMOS33")), ("user_led", 12, Pins("P3"), IOStandard("LVCMOS33")),
("user_led", 13, Pins("N3"), IOStandard("LVCMOS33")), ("user_led", 13, Pins("N3"), IOStandard("LVCMOS33")),
("user_led", 14, Pins("P1"), IOStandard("LVCMOS33")), ("user_led", 14, Pins("P1"), IOStandard("LVCMOS33")),
("user_led", 15, Pins("L1"), IOStandard("LVCMOS33")), ("user_led", 15, Pins("L1"), IOStandard("LVCMOS33")),
# Switches # Switches
("user_sw", 0, Pins("V17"), IOStandard("LVCMOS33")), ("user_sw", 0, Pins("V17"), IOStandard("LVCMOS33")),
@ -43,12 +43,12 @@ _io = [
("user_sw", 7, Pins("W13"), IOStandard("LVCMOS33")), ("user_sw", 7, Pins("W13"), IOStandard("LVCMOS33")),
("user_sw", 8, Pins("V2"), IOStandard("LVCMOS33")), ("user_sw", 8, Pins("V2"), IOStandard("LVCMOS33")),
("user_sw", 9, Pins("T3"), IOStandard("LVCMOS33")), ("user_sw", 9, Pins("T3"), IOStandard("LVCMOS33")),
("user_sw", 10, Pins("T2"), IOStandard("LVCMOS33")), ("user_sw", 10, Pins("T2"), IOStandard("LVCMOS33")),
("user_sw", 11, Pins("R3"), IOStandard("LVCMOS33")), ("user_sw", 11, Pins("R3"), IOStandard("LVCMOS33")),
("user_sw", 12, Pins("W2"), IOStandard("LVCMOS33")), ("user_sw", 12, Pins("W2"), IOStandard("LVCMOS33")),
("user_sw", 13, Pins("U1"), IOStandard("LVCMOS33")), ("user_sw", 13, Pins("U1"), IOStandard("LVCMOS33")),
("user_sw", 14, Pins("T1"), IOStandard("LVCMOS33")), ("user_sw", 14, Pins("T1"), IOStandard("LVCMOS33")),
("user_sw", 15, Pins("R2"), IOStandard("LVCMOS33")), ("user_sw", 15, Pins("R2"), IOStandard("LVCMOS33")),
# Buttons # Buttons
("user_btnu", 0, Pins("T18"), IOStandard("LVCMOS33")), ("user_btnu", 0, Pins("T18"), IOStandard("LVCMOS33")),
@ -85,10 +85,10 @@ _io = [
# Connectors --------------------------------------------------------------------------------------- # Connectors ---------------------------------------------------------------------------------------
_connectors = [ _connectors = [
("pmoda", "J1 L2 J2 G2 H1 K2 H2 G3"), ("pmoda", "J1 L2 J2 G2 H1 K2 H2 G3"),
("pmodb", "A14 A16 B15 B16 A15 A17 C15 C16"), ("pmodb", "A14 A16 B15 B16 A15 A17 C15 C16"),
("pmodc", "K17 M18 N17 P18 L17 M19 P17 R18"), ("pmodc", "K17 M18 N17 P18 L17 M19 P17 R18"),
("pmodxdac", "J3 L3 M2 N2 K3 M3 M1 N1"), ("pmodxdac", " J3 L3 M2 N2 K3 M3 M1 N1"),
] ]
# PMODS -------------------------------------------------------------------------------------------- # PMODS --------------------------------------------------------------------------------------------
@ -129,4 +129,4 @@ class Platform(XilinxPlatform):
def do_finalize(self, fragment): def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment) XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6) self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)

48
litex_boards/targets/digilent_basys3.py Normal file → Executable file
View File

@ -1,3 +1,5 @@
#!/usr/bin/env python3
# #
# This file is part of LiteX-Boards. # This file is part of LiteX-Boards.
# #
@ -6,7 +8,6 @@
import os import os
import argparse import argparse
from litex.build.xilinx import platform
from migen import * from migen import *
@ -19,38 +20,27 @@ from litex.soc.integration.builder import *
from litex.soc.cores.video import VideoVGAPHY from litex.soc.cores.video import VideoVGAPHY
from litex.soc.cores.led import LedChaser from litex.soc.cores.led import LedChaser
from litedram.modules import MT47H64M16
from litedram.phy import s7ddrphy
from liteeth.phy.rmii import LiteEthPHYRMII
# CRG ---------------------------------------------------------------------------------------------- # CRG ----------------------------------------------------------------------------------------------
class _CRG(Module): class _CRG(Module):
def __init__(self, platform, sys_clk_freq): def __init__(self, platform, sys_clk_freq):
self.rst = Signal() self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_idelay = ClockDomain()
self.clock_domains.cd_vga = ClockDomain(reset_less=True) self.clock_domains.cd_vga = ClockDomain(reset_less=True)
self.submodules.pll = pll = S7MMCM(speedgrade=-1) self.submodules.pll = pll = S7MMCM(speedgrade=-1)
self.comb += pll.reset.eq(~platform.request("user_btnc") | self.rst) self.comb += pll.reset.eq(~platform.request("user_btnc") | self.rst)
pll.register_clkin(platform.request("clk100"), 100e6) pll.register_clkin(platform.request("clk100"), 100e6)
pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) pll.create_clkout(self.cd_vga, 40e6)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
pll.create_clkout(self.cd_idelay, 200e6) #platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk100_IBUF]")
pll.create_clkout(self.cd_vga, 40e6)
platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(75e6), with_video_terminal=False, with_video_framebuffer=False, **kwargs): def __init__(self, sys_clk_freq=int(75e6), with_video_terminal=False, **kwargs):
platform = basys3.Platform() platform = basys3.Platform()
# SoCCore ----------------------------------_----------------------------------------------- # SoCCore ----------------------------------_-----------------------------------------------
@ -62,13 +52,13 @@ class BaseSoC(SoCCore):
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq) self.submodules.crg = _CRG(platform, sys_clk_freq)
if with_video_terminal or with_video_framebuffer: # Video ------------------------------------------------------------------------------------
if with_video_terminal:
self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga") self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga")
if with_video_terminal: if with_video_terminal:
self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga") self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser( self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"), pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)
@ -76,16 +66,15 @@ class BaseSoC(SoCCore):
# Build -------------------------------------------------------------------------------------------- # Build --------------------------------------------------------------------------------------------
def main(): def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Basys3") parser = argparse.ArgumentParser(description="LiteX SoC on Basys3")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default: 75MHz)") parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default: 75MHz)")
sdopts = parser.add_mutually_exclusive_group() sdopts = parser.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support") sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
parser.add_argument("--sdcard-adapter", type=str, help="SDCard PMOD adapter: digilent (default) or numato") parser.add_argument("--sdcard-adapter", type=str, help="SDCard PMOD adapter: digilent (default) or numato")
viopts = parser.add_mutually_exclusive_group() viopts = parser.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA)") viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA)")
viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (VGA)")
builder_args(parser) builder_args(parser)
soc_core_args(parser) soc_core_args(parser)
args = parser.parse_args() args = parser.parse_args()
@ -93,7 +82,6 @@ def main():
soc = BaseSoC( soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)), sys_clk_freq = int(float(args.sys_clk_freq)),
with_video_terminal = args.with_video_terminal, with_video_terminal = args.with_video_terminal,
with_video_framebuffer = args.with_video_framebuffer,
**soc_core_argdict(args) **soc_core_argdict(args)
) )
soc.platform.add_extension(basys3._sdcard_pmod_io) soc.platform.add_extension(basys3._sdcard_pmod_io)