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basys3: Review/Simplify and fix build.

This commit is contained in:
Florent Kermarrec 2021-05-25 08:44:26 +02:00
parent 25867c4dcb
commit 1c4825e7c4
2 changed files with 36 additions and 48 deletions
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4
litex_boards/platforms/digilent_basys3.py
View File

@ -12,7 +12,7 @@ from litex.build.openocd import OpenOCD
_io = [
# Clk / Rst
("clk100", 0, Pins("W3"), IOStandard("LVCMOS33")),
("clk100", 0, Pins("W5"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("U16"), IOStandard("LVCMOS33")),
@ -88,7 +88,7 @@ _connectors = [
("pmoda", "J1 L2 J2 G2 H1 K2 H2 G3"),
("pmodb", "A14 A16 B15 B16 A15 A17 C15 C16"),
("pmodc", "K17 M18 N17 P18 L17 M19 P17 R18"),
("pmodxdac", "J3 L3 M2 N2 K3 M3 M1 N1"),
("pmodxdac", " J3 L3 M2 N2 K3 M3 M1 N1"),
]
# PMODS --------------------------------------------------------------------------------------------

30
litex_boards/targets/digilent_basys3.py Normal file → Executable file
View File

@ -1,3 +1,5 @@
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
@ -6,7 +8,6 @@
import os
import argparse
from litex.build.xilinx import platform
from migen import *
@ -19,20 +20,12 @@ from litex.soc.integration.builder import *
from litex.soc.cores.video import VideoVGAPHY
from litex.soc.cores.led import LedChaser
from litedram.modules import MT47H64M16
from litedram.phy import s7ddrphy
from liteeth.phy.rmii import LiteEthPHYRMII
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_idelay = ClockDomain()
self.clock_domains.cd_vga = ClockDomain(reset_less=True)
self.submodules.pll = pll = S7MMCM(speedgrade=-1)
@ -40,17 +33,14 @@ class _CRG(Module):
pll.register_clkin(platform.request("clk100"), 100e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_idelay, 200e6)
pll.create_clkout(self.cd_vga, 40e6)
platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
#platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk100_IBUF]")
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(75e6), with_video_terminal=False, with_video_framebuffer=False, **kwargs):
def __init__(self, sys_clk_freq=int(75e6), with_video_terminal=False, **kwargs):
platform = basys3.Platform()
# SoCCore ----------------------------------_-----------------------------------------------
@ -62,13 +52,13 @@ class BaseSoC(SoCCore):
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
if with_video_terminal or with_video_framebuffer:
# Video ------------------------------------------------------------------------------------
if with_video_terminal:
self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga")
if with_video_terminal:
self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
@ -85,7 +75,6 @@ def main():
parser.add_argument("--sdcard-adapter", type=str, help="SDCard PMOD adapter: digilent (default) or numato")
viopts = parser.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA)")
viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (VGA)")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
@ -93,7 +82,6 @@ def main():
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_video_terminal = args.with_video_terminal,
with_video_framebuffer = args.with_video_framebuffer,
**soc_core_argdict(args)
)
soc.platform.add_extension(basys3._sdcard_pmod_io)