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Merge pull request #160 from antmicro/add-netv2-device-choice

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netv2: add device variant to allow 100T as well
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enjoy-digital 2021-01-28 13:52:28 +01:00 committed by GitHub
commit 1d8f0a9829
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2 changed files with 10 additions and 5 deletions
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9
litex_boards/platforms/netv2.py
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@ -191,9 +191,12 @@ class Platform(XilinxPlatform):
default_clk_name = "clk50" default_clk_name = "clk50"
default_clk_period = 1e9/50e6 default_clk_period = 1e9/50e6
def __init__(self, device="xc7a35t"): def __init__(self, variant="a7-35"):
assert device in ["xc7a35t", "xc7a100t"] device = {
XilinxPlatform.__init__(self, device + "-fgg484-2", _io, toolchain="vivado") "a7-35": "xc7a35t-fgg484-2",
"a7-100": "xc7a100t-fgg484-2"
}[variant]
XilinxPlatform.__init__(self, device, _io, toolchain="vivado")
def create_programmer(self): def create_programmer(self):
bscan_spi = "bscan_spi_xc7a100t.bit" if "xc7a100t" in self.device else "bscan_spi_xc7a35t.bit" bscan_spi = "bscan_spi_xc7a100t.bit" if "xc7a100t" in self.device else "bscan_spi_xc7a35t.bit"

6
litex_boards/targets/netv2.py
View file

@ -62,8 +62,8 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(100e6), with_pcie=False, with_ethernet=False, **kwargs): def __init__(self, variant="a7-35", sys_clk_freq=int(100e6), with_pcie=False, with_ethernet=False, **kwargs):
platform = netv2.Platform() platform = netv2.Platform(variant=variant)
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, SoCCore.__init__(self, platform, sys_clk_freq,
@ -119,6 +119,7 @@ def main():
parser = argparse.ArgumentParser(description="LiteX SoC on NeTV2") parser = argparse.ArgumentParser(description="LiteX SoC on NeTV2")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--variant", default="a7-35", help="Board variant: a7-35 (default) or a7-100")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)") parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)")
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
@ -131,6 +132,7 @@ def main():
args = parser.parse_args() args = parser.parse_args()
soc = BaseSoC( soc = BaseSoC(
variant = args.variant,
sys_clk_freq = int(float(args.sys_clk_freq)), sys_clk_freq = int(float(args.sys_clk_freq)),
with_ethernet = args.with_ethernet, with_ethernet = args.with_ethernet,
with_pcie = args.with_pcie, with_pcie = args.with_pcie,