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partner: add colorlight_5a_75b initial support
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Florent Kermarrec
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07067301d5
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1d9e349093
2 changed files with 264 additions and 0 deletions
153
litex_boards/partner/platforms/colorlight_5a_75b.py
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153
litex_boards/partner/platforms/colorlight_5a_75b.py
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# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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# The Colorlight 5A-75B PCB and IOs have been documented by @miek and @smunaut:
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# https://github.com/q3k/chubby75/tree/master/5a-75b
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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# IOs ----------------------------------------------------------------------------------------------
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_io_v6_1 = [ # Documented by @smunaut
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# clock
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("clk25", 0, Pins("P3"), IOStandard("LVCMOS33")),
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# spi flash (GD25Q16CSIG)
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("spiflash", 0,
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Subsignal("cs_n", Pins("R2")),
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Subsignal("clk", Pins("U3")),
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Subsignal("mosi", Pins("W2")),
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Subsignal("miso", Pins("V2")),
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IOStandard("LVCMOS33"),
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),
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# sdram (EM636165-6G)
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("sdram_clock", 0, Pins("B9"), IOStandard("LVCMOS33")),
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("sdram", 0,
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Subsignal("a", Pins(
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"B13 C14 A16 A17 B16 B15 A14 A13",
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"A12 A11 B12 A11")),
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Subsignal("dq", Pins(
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"D15 E14 E13 D12 E12 D11 C10 B17",
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"B8 A8 C7 A7 A6 B6 A5 B5",
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"D5 C5 D6 C6 E7 D7 E8 D8", # FIXME: D8 was D9
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"E9 D9 E11 C11 C12 D13 D14 C15")),
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Subsignal("we_n", Pins("A10")),
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Subsignal("ras_n", Pins("B10")),
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Subsignal("cas_n", Pins("A9")),
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#Subsignal("cs_n", Pins("")), # gnd
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#Subsignal("cke", Pins("")), # 3v3
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#Subsignal("dm", Pins("")), # gnd
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IOStandard("LVCMOS33"),
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Misc("SLEWRATE=FAST")
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),
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# ethernet (B50612D)
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("eth_clocks", 0,
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Subsignal("tx", Pins("G1")),
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Subsignal("rx", Pins("H2")),
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IOStandard("LVCMOS33")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("P4")),
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Subsignal("mdio", Pins("P5")),
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Subsignal("mdc", Pins("N5")),
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Subsignal("rx_ctl", Pins("P2")),
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Subsignal("rx_data", Pins("K2 L1 N1 P1")),
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Subsignal("tx_ctl", Pins("K1")),
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Subsignal("tx_data", Pins("G2 H1 J1 J3")),
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IOStandard("LVCMOS33")
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),
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("eth_clocks", 1,
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Subsignal("tx", Pins("")),
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Subsignal("rx", Pins("")),
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IOStandard("LVCMOS33")
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),
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("eth", 1,
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Subsignal("rst_n", Pins("P4")),
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Subsignal("mdio", Pins("P5")),
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Subsignal("mdc", Pins("N5")),
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Subsignal("rx_ctl", Pins("L19")),
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Subsignal("rx_data", Pins("P20 N19 N20 N19")),
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Subsignal("tx_ctl", Pins("P19")),
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Subsignal("tx_data", Pins("U20 T19 T20 R20")),
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IOStandard("LVCMOS33")
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),
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]
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_io_v7_0 = [ # Documented by @miek
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# clock
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("clk25", 0, Pins("P6"), IOStandard("LVCMOS33")),
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# led
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("user_led_n", 0, Pins("P11"), IOStandard("LVCMOS33")),
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# btn
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("user_btn_n", 0, Pins("M13"), IOStandard("LVCMOS33")),
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# sdram (M12616161A)
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("sdram_clock", 0, Pins("B9"), IOStandard("LVCMOS33")),
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("sdram", 0,
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Subsignal("a", Pins(
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"A9 E10 B12 D13 C1 D11 D10 E9",
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"D9 B7 C8")),
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Subsignal("dq", Pins(
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"B13 C11 C10 A11 C9 E8 B6 B9",
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"A6 B5 A5 B4 B3 C3 A2 B2",
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"E2 D3 A4 E4 D4 C4 E5 D5",
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"E6 D6 D8 A8 B8 B10 B11 E11")),
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Subsignal("we_n", Pins("C7")),
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Subsignal("ras_n", Pins("D7")),
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Subsignal("cas_n", Pins("E7")),
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#Subsignal("cs_n", Pins("")), # gnd
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#Subsignal("cke", Pins("")), # 3v3
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Subsignal("ba", Pins("A7")),
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#Subsignal("dm", Pins("")), # gnd
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IOStandard("LVCMOS33"),
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Misc("SLEWRATE=FAST")
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),
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# ethernet (B50612D)
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("eth_clocks", 0,
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Subsignal("tx", Pins("M2")),
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Subsignal("rx", Pins("P5")), # FIXME: already used for rst_n
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IOStandard("LVCMOS33")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("P5")),
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Subsignal("mdio", Pins("T2")),
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Subsignal("mdc", Pins("P3")),
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Subsignal("rx_ctl", Pins("N6")),
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Subsignal("rx_data", Pins("N1 M5 N5 M6")),
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Subsignal("tx_ctl", Pins("M3")),
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Subsignal("tx_data", Pins("L1 L3 P2 L4")),
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IOStandard("LVCMOS33")
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),
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("eth_clocks", 1,
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Subsignal("tx", Pins("M12")),
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Subsignal("rx", Pins("M16")),
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IOStandard("LVCMOS33")
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),
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("eth", 1,
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Subsignal("rst_n", Pins("P5")),
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Subsignal("mdio", Pins("T2")),
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Subsignal("mdc", Pins("P3")),
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Subsignal("rx_ctl", Pins("L15")),
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Subsignal("rx_data", Pins("P13 N13 P14 M15")),
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Subsignal("tx_ctl", Pins("R15")),
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Subsignal("tx_data", Pins("T14 R12 R13 R14")),
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IOStandard("LVCMOS33")
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticePlatform):
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def __init__(self, revision="7.0"):
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assert revision in ["6.1", "7.0"]
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self.revision = revision
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device = {"6.1": "LFE5U-25F-6BG381C", "7.0": "LFE5U-25F-6BG256C"}[revision]
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io = {"6.1": _io_v6_1, "7.0": _io_v7_0}[revision]
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LatticePlatform.__init__(self, device, io, toolchain="trellis")
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111
litex_boards/partner/targets/colorlight_5a_75b.py
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111
litex_boards/partner/targets/colorlight_5a_75b.py
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@ -0,0 +1,111 @@
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#!/usr/bin/env python3
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# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import argparse
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import sys
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import colorlight_5a_75b
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
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from liteeth.core import LiteEthUDPIPCore
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from liteeth.frontend.etherbone import LiteEthEtherbone
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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# # #
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# Clk / Rst
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clk25 = platform.request("clk25")
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rst_n = Signal(reset=1)
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if platform.revision in ["7.0"]:
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self.comb += rst_n.eq(platform.request("user_btn_n", 0))
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platform.add_period_constraint(clk25, 1e9/25e6)
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# PLL
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self.submodules.pll = pll = ECP5PLL()
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pll.register_clkin(clk25, 25e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | ~rst_n)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCMini):
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def __init__(self, revision, **kwargs):
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platform = colorlight_5a_75b.Platform(revision=revision)
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sys_clk_freq = int(125e6)
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# SoCMini ----------------------------------------------------------------------------------
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SoCMini.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# Led --------------------------------------------------------------------------------------
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led_counter = Signal(32)
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self.sync += led_counter.eq(led_counter + 1)
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self.comb += platform.request("user_led_n", 0).eq(led_counter[26])
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# EtherboneSoC -------------------------------------------------------------------------------------
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class EtherboneSoC(BaseSoC):
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def __init__(self, eth_phy=0, **kwargs):
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BaseSoC.__init__(self, **kwargs)
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# Ethernet ---------------------------------------------------------------------------------
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# phy
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self.submodules.ethphy = LiteEthPHYRGMII(
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clock_pads = self.platform.request("eth_clocks", eth_phy),
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pads = self.platform.request("eth", eth_phy))
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self.add_csr("ethphy")
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# core
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self.submodules.ethcore = LiteEthUDPIPCore(
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phy = self.ethphy,
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mac_address = 0x10e2d5000000,
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ip_address = "192.168.1.50",
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clk_freq = self.clk_freq)
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# etherbone
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self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234)
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self.add_wb_master(self.etherbone.wishbone.bus)
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# timing constraints
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self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
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self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
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self.platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.ethphy.crg.cd_eth_rx.clk,
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self.ethphy.crg.cd_eth_tx.clk)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Colorlight 5A-75B")
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builder_args(parser)
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soc_core_args(parser)
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parser.add_argument("--revision", default="7.0", type=str, help="Board revision 7.0 (default) or 6.1")
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parser.add_argument("--with-etherbone", action="store_true", help="enable Etherbone support")
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parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY 0 or 1 (default=0)")
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args = parser.parse_args()
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if args.with_etherbone:
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soc = EtherboneSoC(eth_phy=args.eth_phy, revision=args.revision, **soc_core_argdict(args))
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else:
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soc = BaseSoC(args.revision, **soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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if __name__ == "__main__":
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main()
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