Merge pull request #254 from ombhilare999/master
beaglewire platform and target added
This commit is contained in:
enjoy-digital
GitHub
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1e1f6a476d
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#
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# This file is part of LiteX-Boards.
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# Copyright (c) 2021 Omkar Bhilare <ombhilare999@gmail.com>
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# Copyright (c) 2021 Michael Welling <mwelling@ieee.org>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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from litex.build.lattice.programmer import TinyProgProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk100", 0, Pins("61"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("28 29 31 32"), IOStandard("LVCMOS33")),
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("user_btn_n", 0, Pins( "25"), IOStandard("LVCMOS33")),
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# SPIFlash
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("spiflash", 0,
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Subsignal("cs_n", Pins("71"), IOStandard("LVCMOS33")),
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Subsignal("clk", Pins("70"), IOStandard("LVCMOS33")),
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Subsignal("mosi", Pins("67"), IOStandard("LVCMOS33")),
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Subsignal("miso", Pins("68"), IOStandard("LVCMOS33")),
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),
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# SDR SDRAM
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("sdram_clock", 0, Pins("93"), IOStandard("LVCMOS33")),
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("sdram", 0,
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Subsignal("a", Pins("118 117 116 101 81 83 90 91 82 84 119 85 87")),
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Subsignal("dq", Pins("96 97 98 99 95 80 79 78")),
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Subsignal("we_n", Pins("128")),
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Subsignal("ras_n", Pins("124")),
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Subsignal("cas_n", Pins("125")),
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Subsignal("cs_n", Pins("122")),
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Subsignal("cke", Pins("88")),
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Subsignal("ba", Pins("121 120")),
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Subsignal("dm", Pins("94")),
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IOStandard("LVCMOS33"), Misc("SLEWRATE=FAST")
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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# A2-H2, Pins 1-13
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# H9-A6, Pins 14-24
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# G1-J2, Pins 25-31
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("GPIO", "37 39 42 44 38 41 43 45"),
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("GPIO1", "47 49 55 60 48 52 56 62"),
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("GPIO2", "107 112 114 129 110 113 115 130"),
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("GPIO3", "7 9 15 12 4 8 10 11"),
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("grove", "73 74 75 76 104 102 106 105")
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]
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# Default peripherals
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serial = [
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("serial", 0,
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Subsignal("tx", Pins("GPIO:0")),
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Subsignal("rx", Pins("GPIO:1")),
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IOStandard("LVCMOS33")
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)
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticePlatform):
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default_clk_name = "clk100"
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default_clk_period = 1e9/100e6
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def __init__(self, toolchain="icestorm"):
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LatticePlatform.__init__(self, "ice40-hx8k-tq144:4k", _io, _connectors, toolchain=toolchain)
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self.add_extension(serial)
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def create_programmer(self):
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return TinyProgProgrammer()
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def do_finalize(self, fragment):
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LatticePlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
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@ -0,0 +1,149 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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# Copyright (c) 2021 Omkar Bhilare <ombhilare999@gmail.com>
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# Copyright (c) 2021 Michael Welling <mwelling@ieee.org>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import sys
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.build.io import DDROutput
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from litex.build.io import CRG
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from litex_boards.platforms import beaglewire
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.spi_flash import SpiFlash
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from litex.soc.cores.clock import iCE40PLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.uart import UARTWishboneBridge
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from litedram import modules as litedram_modules
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from litedram.phy import GENSDRPHY
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from litedram.modules import MT48LC32M8
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from litex.soc.integration.builder import Builder
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from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage
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kB = 1024
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mB = 1024*kB
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_por = ClockDomain(reset_less=True)
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# # #
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# Clk/Rst
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clk100 = platform.request("clk100")
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rst_n = platform.request("user_btn_n")
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# Power On Reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(ClockSignal())
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# PLL
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self.submodules.pll = pll = iCE40PLL()
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self.comb += pll.reset.eq(rst_n) # FIXME: Add proper iCE40PLL reset support and add back | self.rst.
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=False)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked)
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platform.add_period_constraint(self.cd_sys.clk, 1e9/sys_clk_freq)
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# SDRAM clock
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self.specials += DDROutput(0, 1, platform.request("sdram_clock"), ClockSignal("sys"))
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
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def __init__(self, bios_flash_offset, sys_clk_freq=int(50e6), **kwargs):
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platform = beaglewire.Platform()
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# Disable Integrated ROM since too large for iCE40.
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kwargs["integrated_rom_size"] = 0
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kwargs["integrated_sram_size"] = 2*kB
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# Set CPU variant / reset address
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kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
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kwargs["uart_name"] = "crossover"
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Beaglewire",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# Wishbone ---------------------------------------------------------------------------------
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self.submodules.uart_bridge = UARTWishboneBridge(
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platform.request("serial"),
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sys_clk_freq,
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baudrate=115200)
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self.add_wb_master(self.uart_bridge.wishbone)
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# SPI Flash --------------------------------------------------------------------------------
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self.add_spi_flash(mode="1x", dummy_cycles=8)
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# Add ROM linker region --------------------------------------------------------------------
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self.bus.add_region("rom", SoCRegion(
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origin = self.mem_map["spiflash"] + bios_flash_offset,
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size = 32*kB,
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linker = True)
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)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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self.add_csr("leds")
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self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq )
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = MT48LC32M8(sys_clk_freq, "1:1"),
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l2_cache_size = kwargs.get("l2_size", 1024)
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)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Beaglewire")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--bios-flash-offset", default=0x60000, help="BIOS offset in SPI Flash (default: 0x60000)")
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parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)")
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parser.add_argument("--output_dir", default="build", help="Output directory of csr")
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parser.add_argument("--csr_csv", default="build/csr.csv", help="csr.csv")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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bios_flash_offset = args.bios_flash_offset,
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sys_clk_freq = int(float(args.sys_clk_freq)),
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if __name__ == "__main__":
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main()
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