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ocp_tap_timecard: Add initial SMAIOs peripherals to allow using SMA over PCIe DMA or also with direct (and slow) control/visualization with CSR registers.

This commit is contained in:
Florent Kermarrec 2023-01-13 10:08:44 +01:00
parent fc7154a632
commit 1e35d78512
2 changed files with 84 additions and 24 deletions
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34
litex_boards/platforms/ocp_tap_timecard.py
View File

@ -93,28 +93,28 @@ _io = [
# SMAs.
("sma", 0,
Subsignal("in", Pins("Y11"), IOStandard("LVCMOS33"), Misc("PULLDOWN=TRUE")),
Subsignal("in_en", Pins("H15"), IOStandard("LVCMOS33")),
Subsignal("out", Pins("W11"), IOStandard("LVCMOS33"), Misc("DRIVE=16")),
Subsignal("out_en", Pins("J15"), IOStandard("LVCMOS33")),
Subsignal("dat_in", Pins("Y11"), IOStandard("LVCMOS33"), Misc("PULLDOWN=TRUE")),
Subsignal("dat_in_en", Pins("H15"), IOStandard("LVCMOS33")),
Subsignal("dat_out", Pins("W11"), IOStandard("LVCMOS33"), Misc("DRIVE=16")),
Subsignal("dat_out_en", Pins("J15"), IOStandard("LVCMOS33")),
),
("sma", 1,
Subsignal("in", Pins("Y12"), IOStandard("LVCMOS33"), Misc("PULLDOWN=TRUE")),
Subsignal("in_en", Pins("J14"), IOStandard("LVCMOS33")),
Subsignal("out", Pins("W12"), IOStandard("LVCMOS33"), Misc("DRIVE=16")),
Subsignal("out_en", Pins("H14"), IOStandard("LVCMOS33")),
Subsignal("dat_in", Pins("Y12"), IOStandard("LVCMOS33"), Misc("PULLDOWN=TRUE")),
Subsignal("dat_in_en", Pins("J14"), IOStandard("LVCMOS33")),
Subsignal("dat_out", Pins("W12"), IOStandard("LVCMOS33"), Misc("DRIVE=16")),
Subsignal("dat_out_en", Pins("H14"), IOStandard("LVCMOS33")),
),
("sma", 2,
Subsignal("in", Pins("AA21"), IOStandard("LVCMOS33"), Misc("PULLDOWN=TRUE")),
Subsignal("in_en", Pins("K14"), IOStandard("LVCMOS33")),
Subsignal("out", Pins("V10"), IOStandard("LVCMOS33"), Misc("DRIVE=16")),
Subsignal("out_en", Pins("K13"), IOStandard("LVCMOS33")),
Subsignal("dat_in", Pins("AA21"), IOStandard("LVCMOS33"), Misc("PULLDOWN=TRUE")),
Subsignal("dat_in_en", Pins("K14"), IOStandard("LVCMOS33")),
Subsignal("dat_out", Pins("V10"), IOStandard("LVCMOS33"), Misc("DRIVE=16")),
Subsignal("dat_out_en", Pins("K13"), IOStandard("LVCMOS33")),
),
("sma", 2,
Subsignal("in", Pins("AA20"), IOStandard("LVCMOS33"), Misc("PULLDOWN=TRUE")),
Subsignal("in_en", Pins("L13"), IOStandard("LVCMOS33")),
Subsignal("out", Pins("W10"), IOStandard("LVCMOS33"), Misc("DRIVE=16")),
Subsignal("out_en", Pins("M13"), IOStandard("LVCMOS33")),
("sma", 3,
Subsignal("dat_in", Pins("AA20"), IOStandard("LVCMOS33"), Misc("PULLDOWN=TRUE")),
Subsignal("dat_in_en", Pins("L13"), IOStandard("LVCMOS33")),
Subsignal("dat_out", Pins("W10"), IOStandard("LVCMOS33"), Misc("DRIVE=16")),
Subsignal("dat_out_en", Pins("M13"), IOStandard("LVCMOS33")),
),
]

72
litex_boards/targets/ocp_tap_timecard.py
View File

@ -8,7 +8,7 @@
# Build/Use ----------------------------------------------------------------------------------------
# Build/Load bitstream:
# ./ocp_tap_timecard.py --uart-name=crossover --with-pcie --build --driver --load (or --flash)
# ./ocp_tap_timecard.py --uart-name=crossover --with-pcie --with-smas --build --driver --load (or --flash)
#
#.Build the kernel and load it:
# cd build/<platform>/driver/kernel
@ -32,6 +32,7 @@ from litex.gen import LiteXModule
from litex_boards.platforms import ocp_tap_timecard
from litex.soc.interconnect.csr import *
from litex.soc.interconnect import stream
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
@ -66,6 +67,7 @@ class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=100e6,
with_led_chaser = True,
with_pcie = False,
with_smas = False,
**kwargs):
platform = ocp_tap_timecard.Platform()
@ -82,6 +84,13 @@ class BaseSoC(SoCCore):
self.dna = DNA()
self.dna.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq
)
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
self.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"),
@ -103,13 +112,62 @@ class BaseSoC(SoCCore):
self.flash_cs_n = GPIOOut(platform.request("flash_cs_n"))
self.flash = S7SPIFlash(platform.request("flash"), sys_clk_freq, 25e6)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq
# SMAs -------------------------------------------------------------------------------------
if with_smas:
class SMAIOs(LiteXModule):
def __init__(self, pcie_data_width=64, io_data_width=4):
# Endpoints.
self.sink = stream.Endpoint([("data", pcie_data_width)])
self.source = stream.Endpoint([("data", pcie_data_width)])
# CSRs.
self.control = CSRStorage(fields=[
CSRField("in_en", size=io_data_width, description="Input enable control (1bit per SMA)."),
CSRField("out_en", size=io_data_width, description="Output enable control (1bit per SMA)."),
])
self.output = CSRStorage(io_data_width, description="SMA Reg Output (1bit per SMA).")
self.input = CSRStatus(io_data_width, description="SMA Reg Input (1bit per SMA).")
# # #
# SMA Pads.
sma_pads = [platform.request("sma", i) for i in range(io_data_width)]
# SMA Buffer Control.
for i in range(io_data_width):
self.sync += sma_pads[i].dat_in_en.eq( self.control.fields.in_en)
self.sync += sma_pads[i].dat_out_en.eq(self.control.fields.in_en)
# SMA TX Reg, allow direct (and slow...) control of SMA IOs.
for i in range(io_data_width):
self.sync += If(self.output.storage[i],
sma_pads[i].dat_out.eq(1)
)
# SMA TX Data Pipeline.
self.tx_converter = tx_converter = stream.Converter(pcie_data_width, io_data_width)
self.comb += self.sink.connect(self.tx_converter.sink)
self.comb += self.tx_converter.source.ready.eq(1)
for i in range(io_data_width):
self.sync += If(tx_converter.source.valid & tx_converter.source.data[i],
sma_pads[i].dat_out.eq(1)
)
# SMA RX Reg, allow direct (and slow...) visualization of SMA IOs.
for i in range(io_data_width):
self.sync += self.input.status[i].eq(sma_pads[i].dat_in)
# SMA RX Data Pipeline.
self.rx_converter = stream.Converter(io_data_width, pcie_data_width)
self.comb += self.rx_converter.sink.valid.eq(1)
for i in range(io_data_width):
self.sync += self.rx_converter.sink.data[i].eq(sma_pads[i].dat_in)
self.comb += self.rx_converter.source.connect(self.source)
self.smas = SMAIOs(pcie_data_width=64, io_data_width=4)
self.comb += self.pcie_dma0.source.connect(self.smas.sink)
self.comb += self.smas.source.connect(self.pcie_dma0.sink)
# Build --------------------------------------------------------------------------------------------
def main():
@ -118,12 +176,14 @@ def main():
parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.")
parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
parser.add_target_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
parser.add_target_argument("--with-smas", action="store_true", help="Enable SMAs support.")
parser.add_target_argument("--driver", action="store_true", help="Generate PCIe driver.")
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = args.sys_clk_freq,
with_pcie = args.with_pcie,
with_smas = args.with_smas,
**parser.soc_argdict
)