sqrl_acorn: add option to use vivado programmer
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parent
3dbad2ee06
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202b0e3e7d
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@ -12,7 +12,7 @@
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# RHSResearchLLC that are documented at: https://github.com/RHSResearchLLC/NiteFury-and-LiteFury.
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# RHSResearchLLC that are documented at: https://github.com/RHSResearchLLC/NiteFury-and-LiteFury.
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from litex.build.generic_platform import *
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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from litex.build.openocd import OpenOCD
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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# IOs ----------------------------------------------------------------------------------------------
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@ -130,8 +130,12 @@ class Platform(XilinxPlatform):
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["write_cfgmem -force -format bin -interface spix4 -size 16 "
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["write_cfgmem -force -format bin -interface spix4 -size 16 "
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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def create_programmer(self):
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def create_programmer(self, name='openocd'):
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return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7a200t.bit")
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if name == 'openocd':
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return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7a200t.bit")
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elif name == 'vivado':
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# TODO: some board versions may have s25fl128s
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return VivadoProgrammer(flash_part='s25fl256sxxxxxx0-spi-x1_x2_x4')
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def do_finalize(self, fragment):
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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XilinxPlatform.do_finalize(self, fragment)
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