Merge pull request #128 from trabucayre/redpitaya_support
add support for redpitaya14/16
This commit is contained in:
enjoy-digital
GitHub
commit
20903da54a
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Leds
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("user_led", 0, Pins("F16"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("F17"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("G15"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("H15"), IOStandard("LVCMOS33")),
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("user_led", 4, Pins("K14"), IOStandard("LVCMOS33")),
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("user_led", 5, Pins("G14"), IOStandard("LVCMOS33")),
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("user_led", 6, Pins("J15"), IOStandard("LVCMOS33")),
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("user_led", 7, Pins("J14"), IOStandard("LVCMOS33")),
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("dac", 0,
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Subsignal("data",
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Pins("M19 M20 L19 L20 K19 J19 K20 H20 G19 G20 F19 F20 D20 D19"),
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Drive(4), Misc("SLEW SLOW")),
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Subsignal("wrt", Pins("M17"), Drive(8), Misc("SLEW FAST")),
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Subsignal("sel", Pins("N16"), Drive(8), Misc("SLEW FAST")),
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Subsignal("clk", Pins("M18"), Drive(8), Misc("SLEW FAST")),
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Subsignal("rst", Pins("N15"), Drive(8), Misc("SLEW FAST")),
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IOStandard("LVCMOS33"),
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),
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("pwm_dac", 0, Pins("T10"), IOStandard("LVCMOS18"),
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Drive(8), Misc("SLEW FAST")),
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("pwm_dac", 1, Pins("T11"), IOStandard("LVCMOS18"),
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Drive(8), Misc("SLEW FAST")),
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("pwm_dac", 2, Pins("P15"), IOStandard("LVCMOS18"),
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Drive(8), Misc("SLEW FAST")),
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("pwm_dac", 3, Pins("U13"), IOStandard("LVCMOS18"),
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Drive(8), Misc("SLEW FAST")),
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("daisy", 0,
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Subsignal("io0_p", Pins("T12")),
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Subsignal("io0_n", Pins("U12")),
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Subsignal("io1_p", Pins("U14")),
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Subsignal("io1_n", Pins("U15")),
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IOStandard("DIFF_HSTL_I_18"),
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),
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("daisy", 1,
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Subsignal("io0_p", Pins("P14")),
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Subsignal("io0_n", Pins("R14")),
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Subsignal("io1_p", Pins("N18")),
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Subsignal("io1_n", Pins("P19")),
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IOStandard("DIFF_HSTL_I_18"),
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),
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]
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_io_14 = [
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# Clk / Rst
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("clk125", 0,
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Subsignal("p", Pins("U18")),
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Subsignal("n", Pins("U19")),
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IOStandard("DIFF_HSTL_I_18"),
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),
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("adc", 0,
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Subsignal("data_a",
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Pins("Y17 W16 Y16 W15 W14 Y14 W13 V12 V13 T14 T15 V15 T16 V16")),
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Subsignal("data_b",
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Pins("R18 P16 P18 N17 R19 T20 T19 U20 V20 W20 W19 Y19 W18 Y18")),
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Subsignal("cdcs", Pins("V18")),
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IOStandard("LVCMOS18"),
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),
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]
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_io_16 = [
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# Clk / Rst
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("clk122", 0,
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Subsignal("p", Pins("U18")),
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Subsignal("n", Pins("U19")),
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IOStandard("DIFF_HSTL_I_18"),
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),
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("adc", 0,
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Subsignal("data_a",
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Pins("V17 U17 Y17 W16 Y16 W15 W14 Y14 W13 V12 V13 T14 T15 V15 T16 V16")),
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Subsignal("data_b",
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Pins("T17 R16 R18 P16 P18 N17 R19 T20 T19 U20 V20 W20 W19 Y19 W18 Y18")),
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Subsignal("cdcs", Pins("V18")),
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IOStandard("LVCMOS18"),
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),
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]
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_ps7_io = [
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# PS7
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("ps7_clk", 0, Pins(1)),
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("ps7_porb", 0, Pins(1)),
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("ps7_srstb", 0, Pins(1)),
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("ps7_mio", 0, Pins(54)),
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("ps7_ddram", 0,
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Subsignal("addr", Pins(15)),
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Subsignal("ba", Pins(3)),
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Subsignal("cas_n", Pins(1)),
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Subsignal("ck_n", Pins(1)),
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Subsignal("ck_p", Pins(1)),
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Subsignal("cke", Pins(1)),
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Subsignal("cs_n", Pins(1)),
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Subsignal("dm", Pins(4)),
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Subsignal("dq", Pins(32)),
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Subsignal("dqs_n", Pins(4)),
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Subsignal("dqs_p", Pins(4)),
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Subsignal("odt", Pins(1)),
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Subsignal("ras_n", Pins(1)),
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Subsignal("reset_n", Pins(1)),
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Subsignal("we_n", Pins(1)),
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Subsignal("vrn", Pins(1)),
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Subsignal("vrp", Pins(1)),
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),
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]
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_uart_io = [
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("usb_uart", 0,
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Subsignal("tx", Pins("E1:3")),
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Subsignal("rx", Pins("E1:4")),
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IOStandard("LVCMOS33")
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("E1", "- - G17 G18 H16 H17 J18 H18 K17 K18 L14 L15 L16 L17 K16 J16 M14 M15 - - - - - - - -"),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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def __init__(self, board="redpitaya14"):
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if board == "redpitaya14":
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device = "xc7z010clg400-1"
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extension = _io_14
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self.default_clk_name = "clk125"
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self.default_clk_freq = 125e6
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else:
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device = "xc7z020clg400-1"
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extension = _io_16
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self.default_clk_name = "clk122"
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self.default_clk_freq = 122e6
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self.default_clk_period = 1e9/self.default_clk_freq
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XilinxPlatform.__init__(self, device, _io, _connectors, toolchain="vivado")
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self.add_extension(extension)
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self.add_extension(_ps7_io)
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self.add_extension(_uart_io)
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def create_programmer(self):
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return VivadoProgrammer()
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request(self.default_clk_name, loose=True),
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self.default_clk_period)
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@ -0,0 +1,117 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from litex_boards.platforms import redpitaya
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from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
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from litex.soc.interconnect import axi
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, use_ps7_clk=False):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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# # #
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if use_ps7_clk:
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assert sys_clk_freq == 125e6
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self.comb += ClockSignal("sys").eq(ClockSignal("ps7"))
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self.comb += ResetSignal("sys").eq(ResetSignal("ps7") | self.rst)
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else:
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(platform.request(platform.default_clk_name), platform.default_clk_freq)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, board, sys_clk_freq=int(100e6), **kwargs):
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platform = redpitaya.Platform(board)
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if kwargs["uart_name"] == "serial":
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kwargs["uart_name"] = "usb_uart"
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use_ps7_clk = False
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Zebboard",
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ident_version = True,
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**kwargs)
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# Zynq7000 Integration ---------------------------------------------------------------------
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if kwargs.get("cpu_type", None) == "zynq7000":
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# Get and set the pre-generated .xci FIXME: change location? add it to the repository?
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os.system("wget https://kmf2.trabucayre.com/redpitaya_ps7.txt")
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os.makedirs("xci", exist_ok=True)
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os.system("cp redpitaya_ps7.txt xci/redpitaya_ps7.xci")
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self.cpu.set_ps7_xci("xci/redpitaya_ps7.xci")
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# Connect AXI GP0 to the SoC with base address of 0x43c00000 (default one)
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wb_gp0 = wishbone.Interface()
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self.submodules += axi.AXI2Wishbone(
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axi = self.cpu.add_axi_gp_master(),
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wishbone = wb_gp0,
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base_address = 0x43c00000)
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self.add_wb_master(wb_gp0)
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use_ps7_clk = True
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sys_clk_freq = 125e6
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq, use_ps7_clk)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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self.add_csr("leds")
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Zedboard")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)")
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parser.add_argument("--board", default="redpitaya14", help="Board type: redpitaya14 (default) or redpitaya16")
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builder_args(parser)
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soc_core_args(parser)
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vivado_build_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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board = args.board,
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sys_clk_freq = int(float(args.sys_clk_freq)),
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(**vivado_build_argdict(args), run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"), device=1)
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if __name__ == "__main__":
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main()
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