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Add platform and target files for Antmicro's sdi mipi video converter board 

Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
This commit is contained in:
Tomasz Michalak 2023-01-23 12:13:33 +01:00
parent fdffeb8474
commit 223a69cf91
2 changed files with 369 additions and 0 deletions
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228
litex_boards/platforms/antmicro_sdi_mipi_video_converter.py Normal file
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from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
from litex.build.lattice.programmer import LatticeProgrammer
from litex.build.lattice.programmer import EcpprogProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
("serial", 0,
Subsignal("tx", Pins("J12"), IOStandard("LVCMOS33")),
Subsignal("rx", Pins("J11"), IOStandard("LVCMOS33")),
),
# Section 7.3 General Purpose LEDs
("user_led", 0, Pins("E15"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("E16"), IOStandard("LVCMOS33")),
# Section 7.1 DIP Switch
("user_dip_btn", 0, Pins("F15"), IOStandard("LVCMOS33")),
("user_dip_btn", 1, Pins("H10"), IOStandard("LVCMOS33")),
# Section 6.3.1. SPI Configuration
("spiflash", 0,
Subsignal("cs_n", Pins("C15")),
Subsignal("clk", Pins("C16")),
Subsignal("mosi", Pins("C14")),
Subsignal("miso", Pins("D16")),
IOStandard("LVCMOS33")
)
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = []
# Test and Demo ------------------------------------------------------------------------------------
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticePlatform):
default_clk_name = "clk12"
default_clk_period = 1e9/12e6
def __init__(self, device="LIFCL-40-9BG400C", toolchain="radiant", **kwargs):
# Accept "LIFCL" for backwards compatibility.
# LIFCL just means Crosslink-NX so we can expect every
# Crosslink-NX Evaluation Board to have a LIFCL part.
if device == "LIFCL":
device == "LIFCL-40-9BG400C"
assert device in ["LIFCL-40-9BG256C", "LIFCL-40-9BG400C", "LIFCL-40-8BG400CES", "LIFCL-40-8BG400CES2", "LIFCL-40-8BG400C"]
LatticePlatform.__init__(self, device, _io, _connectors, toolchain=toolchain, **kwargs)
def create_programmer(self, mode = "direct", prog="radiant"):
assert mode in ["direct","flash"]
assert prog in ["radiant","ecpprog"]
if prog == "ecpprog":
return EcpprogProgrammer()
xcf_template_direct = """<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
<ispXCF version="R1.2.0">
<Comment></Comment>
<Chain>
<Comm>JTAG</Comm>
<Device>
<SelectedProg value="TRUE"/>
<Pos>1</Pos>
<Vendor>Lattice</Vendor>
<Family>LIFCL</Family>
<Name>LIFCL-40</Name>
<IDCode>0x010f1043</IDCode>
<Package>All</Package>
<PON>LIFCL-40</PON>
<Bypass>
<InstrLen>8</InstrLen>
<InstrVal>11111111</InstrVal>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
<File>{bitstream_file}</File>
<JedecChecksum>N/A</JedecChecksum>
<MemoryType>Static Random Access Memory (SRAM)</MemoryType>
<Operation>Fast Configuration</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<IOState>HighZ</IOState>
<PreloadLength>362</PreloadLength>
<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
<Usercode>0x00000000</Usercode>
<AccessMode>Direct Programming</AccessMode>
</Option>
</Device>
</Chain>
<ProjectOptions>
<Program>SEQUENTIAL</Program>
<Process>ENTIRED CHAIN</Process>
<OperationOverride>No Override</OperationOverride>
<StartTAP>TLR</StartTAP>
<EndTAP>TLR</EndTAP>
<VerifyUsercode value="FALSE"/>
<TCKDelay>3</TCKDelay>
</ProjectOptions>
<CableOptions>
<CableName>USB2</CableName>
<PortAdd>FTUSB-0</PortAdd>
</CableOptions>
</ispXCF>
"""
xcf_template_flash = """<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
<ispXCF version="R1.2.0">
<Comment></Comment>
<Chain>
<Comm>JTAG2SPI</Comm>
<Device>
<SelectedProg value="TRUE"/>
<Pos>1</Pos>
<Vendor>Lattice</Vendor>
<Family>LIFCL</Family>
<Name>LIFCL-40</Name>
<Package>All</Package>
<Bypass>
<InstrLen>8</InstrLen>
<InstrVal>11111111</InstrVal>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
<File>{bitstream_file}</File>
<MemoryType>External SPI Flash Memory (SPI FLASH)</MemoryType>
<Operation>Erase,Program,Verify</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<Usercode>0x00000000</Usercode>
<AccessMode>Direct Programming</AccessMode>
</Option>
<FPGALoader>
<CPLDDevice>
<Device>
<Pos>1</Pos>
<Vendor>Lattice</Vendor>
<Family>LIFCL</Family>
<Name>LIFCL-40</Name>
<IDCode>0x010f1043</IDCode>
<Package>All</Package>
<PON>LIFCL-40</PON>
<Bypass>
<InstrLen>8</InstrLen>
<InstrVal>11111111</InstrVal>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
<MemoryType>Static Random Access Memory (SRAM)</MemoryType>
<Operation>Refresh Verify ID</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<IOState>HighZ</IOState>
<PreloadLength>362</PreloadLength>
<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
<AccessMode>Direct Programming</AccessMode>
</Option>
</Device>
</CPLDDevice>
<FlashDevice>
<Device>
<Pos>1</Pos>
<Vendor>Macronix</Vendor>
<Family>SPI Serial Flash</Family>
<Name>MX25L12833F</Name>
<IDCode>0x18</IDCode>
<Package>8-pin SOP</Package>
<Operation>Erase,Program,Verify</Operation>
<File>{bitstream_file}</File>
<AddressBase>0x00000000</AddressBase>
<EndAddress>0x000F0000</EndAddress>
<DeviceSize>128</DeviceSize>
<DataSize>1016029</DataSize>
<NumberOfDevices>1</NumberOfDevices>
<ReInitialize value="FALSE"/>
</Device>
</FlashDevice>
<FPGADevice>
<Device>
<Pos>1</Pos>
<Name></Name>
<File>{bitstream_file}</File>
<LocalChainList>
<LocalDevice index="-99"
name="Unknown"
file="{bitstream_file}"/>
</LocalChainList>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
</Option>
</Device>
</FPGADevice>
</FPGALoader>
</Device>
</Chain>
<ProjectOptions>
<Program>SEQUENTIAL</Program>
<Process>ENTIRED CHAIN</Process>
<OperationOverride>No Override</OperationOverride>
<StartTAP>TLR</StartTAP>
<EndTAP>TLR</EndTAP>
<DisableCheckBoard value="TRUE"/>
<VerifyUsercode value="FALSE"/>
<TCKDelay>3</TCKDelay>
</ProjectOptions>
<CableOptions>
<CableName>USB2</CableName>
<PortAdd>FTUSB-0</PortAdd>
<USBID>Lattice CrossLink-NX Eval Board A Location 0000 Serial FT4J4IK9A</USBID>
</CableOptions>
</ispXCF>
"""
if mode == "direct":
xcf_template = xcf_template_direct
if mode == "flash":
xcf_template = xcf_template_flash
return LatticeProgrammer(xcf_template)

141
litex_boards/targets/antmicro_sdi_mipi_video_converter.py Executable file
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#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2023 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
import os
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
import platforms.antmicro_sdi_mipi_video_converter
from litex.soc.cores.ram import NXLRAM
from litex.soc.cores.clock import NXPLL
from litex.build.io import CRG
from litex.build.generic_platform import *
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser
from litex.build.lattice.oxide import oxide_args, oxide_argdict
from litex.build.lattice.radiant import radiant_build_argdict, radiant_build_args
kB = 1024
mB = 1024*kB
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_por = ClockDomain()
self.clock_domains.cd_sys = ClockDomain()
# Built in OSC
self.submodules.hf_clk = NXOSCA()
hf_clk_freq = 25e6
self.hf_clk.create_hf_clk(self.cd_por, hf_clk_freq)
# Power on reset
por_count = Signal(16, reset=2**16-1)
por_done = Signal()
self.comb += por_done.eq(por_count == 0)
self.sync.por += If(~por_done, por_count.eq(por_count - 1))
# PLL
self.submodules.sys_pll = sys_pll = NXPLL(platform=platform, create_output_port_clocks=True)
sys_pll.register_clkin(self.cd_por.clk, hf_clk_freq)
sys_pll.create_clkout(self.cd_sys, sys_clk_freq)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~self.sys_pll.locked | ~por_done )
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
mem_map = {
"rom" : 0x00000000,
"sram" : 0x40000000,
"main_ram": 0x60000000,
"csr" : 0xf0000000,
}
def __init__(self, sys_clk_freq=int(75e6), device="LIFCL-40-9BG256C", toolchain="radiant", with_led_chaser=True, **kwargs):
platform = antmicro_sdi_mipi_video_converter.Platform(device=device, toolchain=toolchain)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SoCCore -----------------------------------------_----------------------------------------
# Disable Integrated SRAM since we want to instantiate LRAM specifically for it
kwargs["integrated_sram_size"] = 0
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Crosslink-NX Evaluation Board", **kwargs)
# 128KB LRAM (used as SRAM) ---------------------------------------------------------------
self.submodules.spram = NXLRAM(32, 64*kB)
self.register_mem("sram", self.mem_map["sram"], self.spram.bus, 16*kB)
self.submodules.main_ram = NXLRAM(32, 64*kB)
self.register_mem("main_ram", self.mem_map["main_ram"], self.main_ram.bus, 64*kB)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = Cat(*[platform.request("user_led", i) for i in range(2)]),
sys_clk_freq = sys_clk_freq)
# Build --------------------------------------------------------------------------------------------
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Crosslink-NX Eval Board")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build design.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--toolchain", default="radiant", help="FPGA toolchain (radiant or prjoxide).")
target_group.add_argument("--device", default="LIFCL-40-9BG256C", help="FPGA device (LIFCL-40-9BG400C, LIFCL-40-8BG400CES, or LIFCL-40-8BG400CES2).")
target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
target_group.add_argument("--programmer", default="radiant", help="Programmer (radiant or ecpprog).")
target_group.add_argument("--prog-target", default="direct", help="Programming Target (direct or flash).")
builder_args(parser)
soc_core_args(parser)
oxide_args(parser)
radiant_build_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
device = args.device,
toolchain = args.toolchain,
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder_kargs = oxide_argdict(args) if args.toolchain == "oxide" else radiant_build_argdict(args)
if args.build:
builder.build(**builder_kargs)
if args.load:
prog = soc.platform.create_programmer(args.prog_target, args.programmer)
if args.programmer == "ecpprog" and args.prog_target == "flash":
prog.flash(address=args.address, bitstream=builder.get_bitstream_filename(mode="sram"))
else:
if args.programmer == "radiant":
os.system("sudo modprobe -rf ftdi_sio")
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if args.programmer == "radiant":
os.system("sudo modprobe ftdi_sio")
if __name__ == "__main__":
main()