qmtech_10cl001: fix wrong sdram clock pin

2021-11-15 09:53:46 +07:00 · 2021-11-15 09:53:46 +07:00 · 2272962315
parent 138dc1467e
commit 2272962315
1 changed files with 1 additions and 1 deletions
--- a/litex_boards/platforms/qmtech_10cl006.py
+++ b/litex_boards/platforms/qmtech_10cl006.py
@ -29,7 +29,7 @@ _io = [
    ),

    # SDR SDRAM
-    ("sdram_clock", 0, Pins("Y6"), IOStandard("3.3-V LVTTL")),
+    ("sdram_clock", 0, Pins("P2"), IOStandard("3.3-V LVTTL")),
    ("sdram", 0,
        Subsignal("a",     Pins(
            "R7 T7 R8 T8 R6 T5 R5 T4",