boards: added datacenter DDR4 RDIMM tester board
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
Alessandro Comodi
parent
d5eea94289
commit
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# TODO: change clock when assigned to schematic
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("clk100", 0, Pins("AC23"), IOStandard("LVCMOS33")),
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("user_led", 0, Pins("D21"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("B20"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("B21"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("C22"), IOStandard("LVCMOS33")),
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("user_led", 4, Pins("E22"), IOStandard("LVCMOS33")),
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("user_btn", 0, Pins("C21"), IOStandard("LVCMOS33")),
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("user_btn", 1, Pins("A20"), IOStandard("LVCMOS33")),
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("user_btn", 2, Pins("E21"), IOStandard("LVCMOS33")),
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("user_btn", 3, Pins("D23"), IOStandard("LVCMOS33")),
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("serial", 0,
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Subsignal("tx", Pins("E26")),
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Subsignal("rx", Pins("F25")),
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IOStandard("LVCMOS33")
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),
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("serial", 1,
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Subsignal("tx", Pins("D26")),
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Subsignal("rx", Pins("E25")),
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IOStandard("LVCMOS33")
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),
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# DDR4
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("ddr4", 0,
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Subsignal("a", Pins(
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"AF10 AC11 AD11 AD10 AC9 AD9 AB9 AF7 AE8",
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"AE7 Y12 AC7 AB7 AD13"),
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IOStandard("SSTL12_DCI")),
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Subsignal("ba", Pins("AB11 AB10"), IOStandard("SSTL12_DCI")),
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Subsignal("bg", Pins("AA9 AF9"), IOStandard("SSTL12_DCI")),
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Subsignal("ras_n", Pins("AA12"), IOStandard("SSTL12_DCI")), # A16
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Subsignal("cas_n", Pins("AF13"), IOStandard("SSTL12_DCI")), # A15
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Subsignal("we_n", Pins("AA13"), IOStandard("SSTL12_DCI")), # A14
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Subsignal("cs_n", Pins("W13 AA14 AC14 AF15"), IOStandard("SSTL12_DCI")),
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Subsignal("act_n", Pins("Y8"), IOStandard("SSTL12_DCI")),
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Subsignal("alert_n", Pins("AE10"), IOStandard("SSTL12_DCI")),
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Subsignal("par", Pins("AE13"), IOStandard("SSTL12_DCI")),
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Subsignal("dm", Pins("AF3 AE5 AD6 AC6 AF2 AE3 AE6 AD5"),
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IOStandard("SSTL12_DCI")),
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Subsignal("dq", Pins(
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"W11 Y11 V7 Y7 V11 V9 V8 W8",
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"U2 V6 Y2 Y3 U5 U4 W3 Y1",
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"AA2 AB2 AE1 AE2 V2 W1 AD1 AC2",
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"W4 AA3 AD3 AC4 V3 V4 AB4 AC3",
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"AC16 AC17 AB16 AA19 AB15 AD16 AC18 AC19",
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"AF17 AE17 AF20 AD19 AE15 AE16 AF19 AD18",
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"Y18 Y17 W14 V14 AA20 AA15 V18 W16",
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"AA18 AB19 V16 W15 AB17 AA17 V19 V17"),
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IOStandard("SSTL12")),
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Subsignal("dqs_p", Pins(
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"W10 W6 AB1 AA5 AD20 AE18 W18 Y15 AF5",
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"B17 D19 L19 J15 T24 P19 R16 M25 AC8"),
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IOStandard("DIFF_HSUL_12")),
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Subsignal("dqs_n", Pins(
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"W9 W5 AC1 AB5 AE20 AF18 W19 Y16 AF4",
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"A17 D20 L20 J16 T25 P20 R17 L25 AD8"),
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IOStandard("DIFF_HSUL_12")),
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Subsignal("clk_p", Pins("AE12 AB12"), IOStandard("DIFF_SSTL12_DCI")),
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Subsignal("clk_n", Pins("AF12 AC12"), IOStandard("DIFF_SSTL12_DCI")),
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Subsignal("cke", Pins("AA8 AA7"), IOStandard("SSTL12_DCI")), # also AM15 for larger SODIMMs
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Subsignal("odt", Pins("Y13 AB14"), IOStandard("SSTL12_DCI")), # also AM16 for larger SODIMMs
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Subsignal("reset_n", Pins("AB6"), IOStandard("SSTL12")),
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Misc("SLEW=FAST"),
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),
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# RGMII Ethernet
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("eth_ref_clk", 0, Pins("AA23"), IOStandard("LVCMOS33")),
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("eth_clocks", 0,
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Subsignal("tx", Pins("Y23")),
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Subsignal("rx", Pins("AA24")),
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IOStandard("LVCMOS33")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("AA22")),
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Subsignal("mdio", Pins("AB26")),
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Subsignal("mdc", Pins("AA25")),
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Subsignal("rx_ctl", Pins("Y25")),
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Subsignal("rx_data", Pins("W26 W25 V26 U25")),
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Subsignal("tx_ctl", Pins("U26")),
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Subsignal("tx_data", Pins("W24 Y26 Y22 Y21")),
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IOStandard("LVCMOS33")
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),
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# HyperRAM
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("hyperram", 0,
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Subsignal("clk_n", Pins("AE26")),
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Subsignal("clk_p", Pins("AD26")),
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Subsignal("rst_n", Pins("AC24")),
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Subsignal("cs_n", Pins("AC26")),
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Subsignal("dq", Pins("AE23 AD25 AF24 AE22 AF23 AF25 AE25 AD24")),
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Subsignal("rwds", Pins("AD23")),
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IOStandard("LVCMOS33")
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),
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# SD Card
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("sdcard", 0,
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Subsignal("data", Pins("E10 F8 C9 D9"), Misc("PULLUP True")),
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Subsignal("cmd", Pins("D8"), Misc("PULLUP True")),
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Subsignal("clk", Pins("D10")),
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Subsignal("cd", Pins("F9")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS33"),
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk100"
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default_clk_period = 1e9/100e6
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def __init__(self, device="xc7k160tffg676-1"):
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XilinxPlatform.__init__(self, device, _io, toolchain="vivado")
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix4 -size 16 "
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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self.add_platform_command("set_property INTERNAL_VREF 0.6 [get_iobanks 32]")
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self.add_platform_command("set_property INTERNAL_VREF 0.6 [get_iobanks 33]")
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self.add_platform_command("set_property INTERNAL_VREF 0.6 [get_iobanks 34]")
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def create_programmer(self):
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return OpenOCD("openocd_xc7_ft4232.cfg", "bscan_spi_xc7k100t.bit")
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
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@ -0,0 +1,172 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from litex_boards.platforms import datacenter_ddr4_test_board
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from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MTA18ASF2G72PZ
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from litedram.phy.s7ddrphy import K7DDRPHY
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from liteeth.phy import LiteEthS7PHYRGMII
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from litehyperbus.core.hyperbus import HyperRAM
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, iodelay_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_idelay = ClockDomain()
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# # #
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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pll.register_clkin(platform.request("clk100"), 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys2x, 2 * sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4 * sys_clk_freq)
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pll.create_clkout(self.cd_idelay, iodelay_clk_freq)
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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mem_map = {
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"hyperram": 0x20000000,
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}
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mem_map.update(SoCCore.mem_map)
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def __init__(self, *, sys_clk_freq=int(100e6), iodelay_clk_freq=200e6,
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with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
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with_hyperram=False, with_sdcard=False, with_jtagbone=True, with_uartbone=False,
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with_led_chaser=True, ident_version=True, **kwargs):
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platform = datacenter_ddr4_test_board.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on data center test board",
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ident_version = ident_version,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq, iodelay_clk_freq=iodelay_clk_freq)
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# DDR4 SDRAM RDIMM -------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = K7DDRPHY(platform.request("ddr4"),
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memtype = "DDR4",
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iodelay_clk_freq = iodelay_clk_freq,
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sys_clk_freq = sys_clk_freq,
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is_rdimm = True,
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)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MTA18ASF2G72PZ(sys_clk_freq, "1:4"),
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l2_cache_size = kwargs.get("l2_size", 8192),
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l2_cache_min_data_width = 256,
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size = 0x40000000,
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)
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# HyperRAM ---------------------------------------------------------------------------------
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if with_hyperram:
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self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
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self.register_mem("hyperram", self.mem_map["hyperram"], self.hyperram.bus, 8*1024*1024)
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# SD Card ----------------------------------------------------------------------------------
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if with_sdcard:
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self.add_sdcard()
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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# Traces between PHY and FPGA introduce ignorable delays of ~0.165ns +/- 0.015ns.
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# PHY chip does not introduce delays on TX (FPGA->PHY), however it includes 1.2ns
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# delay for RX CLK so we only need 0.8ns to match the desired 2ns.
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self.submodules.ethphy = LiteEthS7PHYRGMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"),
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rx_delay = 0.8e-9,
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)
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if with_ethernet:
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self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
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# UartBone ---------------------------------------------------------------------------------
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if with_uartbone:
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self.add_uartbone("serial", baudrate=1e6)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on LPDDR4 Test Board")
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target = parser.add_argument_group(title="Target options")
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target.add_argument("--build", action="store_true", help="Build bitstream")
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target.add_argument("--load", action="store_true", help="Load bitstream")
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target.add_argument("--flash", action="store_true", help="Flash bitstream")
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target.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency")
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target.add_argument("--iodelay-clk-freq", default=200e6, help="IODELAYCTRL frequency")
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ethopts = target.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Add Ethernet")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Add EtherBone")
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target.add_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address")
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target.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting")
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target.add_argument("--with-hyperram", action="store_true", help="Add HyperRAM")
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target.add_argument("--with-sdcard", action="store_true", help="Add SDCard")
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target.add_argument("--with-jtagbone", action="store_true", help="Add JTAGBone")
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target.add_argument("--with-uartbone", action="store_true", help="Add UartBone on 2nd serial")
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parser.add_argument("--no-ident-version", action="store_false", help="Disable build time output")
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builder_args(parser)
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soc_core_args(parser)
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vivado_build_args(parser)
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args = parser.parse_args()
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assert not (args.with_etherbone and args.eth_dynamic_ip)
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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iodelay_clk_freq = int(float(args.iodelay_clk_freq)),
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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eth_ip = args.eth_ip,
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eth_dynamic_ip = args.eth_dynamic_ip,
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with_hyperram = args.with_hyperram,
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with_sdcard = args.with_sdcard,
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with_jtagbone = args.with_jtagbone,
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with_uartbone = args.with_uartbone,
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ident_version = args.no_ident_version,
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**soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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vns = builder.build(**vivado_build_argdict(args), run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if args.flash:
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prog = soc.platform.create_programmer()
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prog.flash(0, os.path.join(builder.gateware_dir, soc.build_name + ".bin"))
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if __name__ == "__main__":
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main()
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