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sqrl_acorn: Add flashing/reload support when used with PCIe, fix JTAG flash.

This commit is contained in:
Florent Kermarrec 2021-04-21 17:00:40 +02:00
parent 443b954c0c
commit 228a9650d4
2 changed files with 19 additions and 6 deletions
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4
litex_boards/platforms/sqrl_acorn.py
View File

@ -31,8 +31,8 @@ _io = [
("user_led", 3, Pins("H4"), IOStandard("LVCMOS33")),
# SPIFlash.
("spiflash", 0,
Subsignal("cs_n", Pins("T19")),
("flash_cs_n", 0, Pins("T19"), IOStandard("LVCMOS33")),
("flash", 0,
Subsignal("mosi", Pins("P22")),
Subsignal("miso", Pins("R22")),
Subsignal("wp", Pins("P21")),

21
litex_boards/targets/sqrl_acorn.py
View File

@ -104,11 +104,24 @@ class BaseSoC(SoCCore):
bar0_size = 0x20000)
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# FIXME: Improve (Make it generic and apply it to all targets).
platform.toolchain.pre_placement_commands.append("set_clock_groups -group [get_clocks clkout0] -group [get_clocks userclk2] -asynchronous",)
platform.toolchain.pre_placement_commands.append("set_clock_groups -group [get_clocks clkout0] -group [get_clocks clk_125mhz] -asynchronous")
platform.toolchain.pre_placement_commands.append("set_clock_groups -group [get_clocks clkout0] -group [get_clocks clk_250mhz] -asynchronous")
platform.toolchain.pre_placement_commands.append("set_clock_groups -group [get_clocks main_crg_clkout0] -group [get_clocks userclk2] -asynchronous",)
platform.toolchain.pre_placement_commands.append("set_clock_groups -group [get_clocks main_crg_clkout0] -group [get_clocks clk_125mhz] -asynchronous")
platform.toolchain.pre_placement_commands.append("set_clock_groups -group [get_clocks main_crg_clkout0] -group [get_clocks clk_250mhz] -asynchronous")
platform.toolchain.pre_placement_commands.append("set_clock_groups -group [get_clocks clk_125mhz] -group [get_clocks clk_250mhz] -asynchronous")
# ICAP (For FPGA reload over PCIe).
from litex.soc.cores.icap import ICAP
self.submodules.icap = ICAP()
self.icap.add_reload()
self.icap.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk)
# Flash (For SPIFlash update over PCIe). FIXME: Should probably be updated to use SpiFlashSingle/SpiFlashDualQuad (so MMAPed and do the update with bit-banging)
from litex.soc.cores.gpio import GPIOOut
from litex.soc.cores.spi_flash import S7SPIFlash
self.submodules.flash_cs_n = GPIOOut(platform.request("flash_cs_n"))
self.submodules.flash = S7SPIFlash(platform.request("flash"), sys_clk_freq, 25e6)
# SATA -------------------------------------------------------------------------------------
if with_sata:
from litex.build.generic_platform import Subsignal, Pins
@ -188,7 +201,7 @@ def main():
if args.flash:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bin"))
prog.flash(0, os.path.join(builder.gateware_dir, soc.build_name + ".bin"))
if __name__ == "__main__":
main()