rename ld board prefix to machdyne

This commit is contained in:
inc 2022-07-15 17:13:00 +02:00
parent 3ecec8cd16
commit 22dcadcfa1
4 changed files with 5 additions and 5 deletions

View File

@ -25,7 +25,7 @@ from migen import *
from litex.build.io import CRG from litex.build.io import CRG
from litex_boards.platforms import ld_krote from litex_boards.platforms import machdyne_krote
from litex.soc.integration.soc_core import * from litex.soc.integration.soc_core import *
from litex.soc.integration.soc import SoCRegion from litex.soc.integration.soc import SoCRegion
@ -69,7 +69,7 @@ class _CRG(Module):
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
mem_map = {**SoCCore.mem_map, **{"spiflash": 0x20000000}} mem_map = {**SoCCore.mem_map, **{"spiflash": 0x20000000}}
def __init__(self, bios_flash_offset, sys_clk_freq=int(100e6), with_led_chaser=True, **kwargs): def __init__(self, bios_flash_offset, sys_clk_freq=int(100e6), with_led_chaser=True, **kwargs):
platform = ld_krote.Platform() platform = machdyne_krote.Platform()
# Disable Integrated ROM since too large for iCE40. # Disable Integrated ROM since too large for iCE40.
kwargs["integrated_rom_size"] = 0 kwargs["integrated_rom_size"] = 0

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@ -13,7 +13,7 @@ import sys
import json import json
from migen import * from migen import *
from litex_boards.platforms import ld_schoko from litex_boards.platforms import machdyne_schoko
from litex.build.lattice.trellis import trellis_args, trellis_argdict from litex.build.lattice.trellis import trellis_args, trellis_argdict
from litex.build.io import DDROutput from litex.build.io import DDROutput
@ -105,7 +105,7 @@ class BaseSoC(SoCCore):
}} }}
def __init__(self, revision="v1", device="45F", sdram_rate="1:2", def __init__(self, revision="v1", device="45F", sdram_rate="1:2",
sys_clk_freq=int(40e6), toolchain="trellis", with_led_chaser=True, with_usb_host=False, **kwargs): sys_clk_freq=int(40e6), toolchain="trellis", with_led_chaser=True, with_usb_host=False, **kwargs):
platform = ld_schoko.Platform(revision=revision, device=device ,toolchain=toolchain) platform = machdyne_schoko.Platform(revision=revision, device=device ,toolchain=toolchain)
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate) self.submodules.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate)
@ -176,7 +176,7 @@ def main():
target_group.add_argument("--load", action="store_true", help="Load bitstream to SRAM.") target_group.add_argument("--load", action="store_true", help="Load bitstream to SRAM.")
target_group.add_argument("--flash", action="store_true", help="Flash bitstream to MMOD.") target_group.add_argument("--flash", action="store_true", help="Flash bitstream to MMOD.")
target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).") target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
target_group.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.") target_group.add_argument("--sys-clk-freq", default=40e6, help="System clock frequency.")
target_group.add_argument("--revision", default="v1", help="Board Revision (v1, v2).") target_group.add_argument("--revision", default="v1", help="Board Revision (v1, v2).")
target_group.add_argument("--device", default="45F", help="ECP5 device (25F, 45F or 85F).") target_group.add_argument("--device", default="45F", help="ECP5 device (25F, 45F or 85F).")
target_group.add_argument("--cable", default="usb-blaster", help="Specify an openFPGALoader cable.") target_group.add_argument("--cable", default="usb-blaster", help="Specify an openFPGALoader cable.")