add initial support for kröte fpga board

litex_boards/platforms/ld_krote.py

@@ -0,0 +1,67 @@
+#
+# This file is part of LiteX-Boards.
+# Copyright (c) 2018 William D. Jones <thor0505@comcast.net>
+# Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
+# Copyright (c) 2022 Lone Dynamics Corporation <info@lonedynamics.com>
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+# Krote FPGA board: https://github.com/machdyne/krote
+#
+
+from litex.build.generic_platform import *
+from litex.build.lattice import LatticePlatform
+
+# IOs ----------------------------------------------------------------------------------------------
+
+_io = [
+
+    # Clk / Rst
+    ("clk100", 0, Pins("B6"), IOStandard("LVCMOS33")),
+
+    # Leds
+    ("user_led", 0, Pins("E2 F1 G2 J2"), IOStandard("LVCMOS33")),
+
+    # SPIFlash
+    ("spiflash", 0,
+        Subsignal("cs_n", Pins("K10"), IOStandard("LVCMOS33")),
+        Subsignal("clk",  Pins("L10"), IOStandard("LVCMOS33")),
+        Subsignal("mosi", Pins("K9"), IOStandard("LVCMOS33")),
+        Subsignal("miso", Pins("J9"), IOStandard("LVCMOS33")),
+    ),
+
+]
+
+
+# Connectors ---------------------------------------------------------------------------------------
+
+_connectors = [
+    ("PMODA",  "E1 B1 A2 A4 D1 C1 A1 A3"),
+    ("PMODB",  "L3 L1 H1 G3 L2 K1 J1 F2"),
+    ("PMODC",  "A8 A10 C11 A9 D10 B11 D11"),
+    ("PMODD",  "E9 G10 F10 H11 E11 G11 G9"),
+    ("PMODE",  "L8 K5 K3 L5 L7 K4 K2 L4")
+]
+
+# Default peripherals
+serial = [
+    ("serial", 0,
+        Subsignal("tx", Pins("PMODE:1")),
+        Subsignal("rx", Pins("PMODE:2")),
+        IOStandard("LVCMOS33")
+    )
+]
+
+# Platform -----------------------------------------------------------------------------------------
+
+class Platform(LatticePlatform):
+    default_clk_name   = "clk100"
+    default_clk_period = 1e9/100e6
+
+    def __init__(self, toolchain="icestorm"):
+        LatticePlatform.__init__(self, "ice40-hx8k-bg121", _io, _connectors, toolchain=toolchain)
+        self.add_extension(serial)
+
+    def do_finalize(self, fragment):
+        LatticePlatform.do_finalize(self, fragment)
+        self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)

litex_boards/targets/ld_krote.py

@@ -0,0 +1,128 @@
+#!/usr/bin/env python3
+
+#
+# This file is part of LiteX-Boards.
+#
+# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
+# Copyright (c) 2021 Omkar Bhilare <ombhilare999@gmail.com>
+# Copyright (c) 2021 Michael Welling <mwelling@ieee.org>
+# Copyright (c) 2022 Lone Dynamics Corporation <info@lonedynamics.com>
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+# Krote FPGA board: https://github.com/machdyne/krote
+#
+# TODO:
+# - add support for QQSPI PSRAM (32MB) pmod
+# - add support for SD card pmod 
+#
+
+import os
+import sys
+import argparse
+
+from migen import *
+
+from litex.build.io import CRG
+
+from litex_boards.platforms import ld_krote
+
+from litex.soc.integration.soc_core import *
+from litex.soc.integration.soc import SoCRegion
+from litex.soc.integration.builder import *
+from litex.soc.cores.clock import iCE40PLL
+from litex.soc.cores.led import LedChaser
+
+from migen.genlib.resetsync import AsyncResetSynchronizer
+
+kB = 1024
+mB = 1024*kB
+
+class _CRG(Module):
+    def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
+        self.clock_domains.cd_sys    = ClockDomain()
+        self.clock_domains.cd_por    = ClockDomain(reset_less=True)
+
+        # Clk/Rst
+        clk100 = platform.request("clk100")
+        platform.add_period_constraint(clk100, 1e9/100e6)
+
+        # Power On Reset
+        por_count = Signal(16, reset=2**16-1)
+        por_done  = Signal()
+        self.comb += self.cd_por.clk.eq(clk100)
+        self.comb += por_done.eq(por_count == 0)
+        self.sync.por += If(~por_done, por_count.eq(por_count - 1))
+
+        # Sys Clk
+        self.submodules.pll = pll = iCE40PLL()
+        pll.register_clkin(clk100, 100e6)
+        pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=False)
+        self.specials += AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked)
+        platform.add_period_constraint(self.cd_sys.clk, 1e9/sys_clk_freq)
+
+
+
+# BaseSoC ------------------------------------------------------------------------------------------
+
+class BaseSoC(SoCCore):
+    mem_map = {**SoCCore.mem_map, **{"spiflash": 0x20000000}}
+    def __init__(self, bios_flash_offset, sys_clk_freq=int(100e6), with_led_chaser=True, **kwargs):
+        platform = ld_krote.Platform()
+
+        # Disable Integrated ROM since too large for iCE40.
+        kwargs["integrated_rom_size"]  = 0
+        kwargs["integrated_sram_size"]  = 4*kB
+
+        # Set CPU variant / reset address
+        kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
+
+        # SoCCore ----------------------------------------------------------------------------------
+        SoCCore.__init__(self, platform, sys_clk_freq,
+            ident          = "LiteX SoC on Kr\xf6te",
+            **kwargs)
+
+        # CRG --------------------------------------------------------------------------------------
+        self.submodules.crg = _CRG(platform, sys_clk_freq)
+
+        # SPI Flash --------------------------------------------------------------------------------
+        from litespi.modules import W25Q32
+        from litespi.opcodes import SpiNorFlashOpCodes as Codes
+        self.add_spi_flash(mode="1x", module=W25Q32(Codes.READ_1_1_1), with_master=False)
+
+        # Add ROM linker region --------------------------------------------------------------------
+        self.bus.add_region("rom", SoCRegion(
+            origin = self.mem_map["spiflash"] + bios_flash_offset,
+            size   = 32*kB,
+            linker = True)
+        )
+
+        # Leds -------------------------------------------------------------------------------------
+        if with_led_chaser:
+            self.submodules.leds = LedChaser(
+                pads         = platform.request_all("user_led"),
+                sys_clk_freq = sys_clk_freq)
+
+# Build --------------------------------------------------------------------------------------------
+
+def main():
+    parser = argparse.ArgumentParser(description="LiteX SoC on Kr\xf6te")
+    parser.add_argument("--build",             action="store_true", help="Build bitstream")
+    parser.add_argument("--bios-flash-offset", default="0x021000",  help="BIOS offset in SPI Flash (default: 0x21000)")
+    parser.add_argument("--sys-clk-freq",      default=50e6,        help="System clock frequency (default: 50MHz)")
+    parser.add_argument("--with-led-chaser", action="store_true", help="Enable LED Chaser.")
+    builder_args(parser)
+    soc_core_args(parser)
+    args = parser.parse_args()
+
+    soc = BaseSoC(
+         bios_flash_offset = int(args.bios_flash_offset, 0),
+         sys_clk_freq      = int(float(args.sys_clk_freq)),
+         **soc_core_argdict(args)
+    )
+    builder = Builder(soc, **builder_argdict(args))
+    builder.build(run=args.build)
+
+if __name__ == "__main__":
+    main()