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targets/siglent_sds1104xe: simplify etherbone by using new etherbone's params to specify hybrid mode

This commit is contained in:
Gwenhael Goavec-Merou 2023-10-23 19:07:37 +02:00
parent 16319f5cf0
commit 26d112b094
1 changed files with 14 additions and 35 deletions
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49
litex_boards/targets/siglent_sds1104xe.py
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@ -97,53 +97,32 @@ class BaseSoC(SoCCore):
# Etherbone -------------------------------------------------------------------------------- # Etherbone --------------------------------------------------------------------------------
if with_etherbone: if with_etherbone:
# FIXME: Simplify LiteEth Hybrid MAC integration. from litex.soc.integration.soc import SoCRegion
from liteeth.common import convert_ip
from liteeth.mac import LiteEthMAC
from liteeth.core.arp import LiteEthARP
from liteeth.core.ip import LiteEthIP
from liteeth.core.udp import LiteEthUDP
from liteeth.core.icmp import LiteEthICMP
from liteeth.core import LiteEthUDPIPCore
from liteeth.frontend.etherbone import LiteEthEtherbone
# Ethernet PHY # Ethernet PHY
self.ethphy = LiteEthPHYMII( self.ethphy = LiteEthPHYMII(
clock_pads = self.platform.request("eth_clocks"), clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth")) pads = self.platform.request("eth"))
etherbone_ip_address = convert_ip("192.168.1.51")
etherbone_mac_address = 0x10e2d5000001
# Ethernet MAC self.add_etherbone(
self.ethmac = LiteEthMAC(phy=self.ethphy, dw=8, phy = self.ethphy,
interface = "hybrid", ip_address = "192.168.1.51",
endianness = self.cpu.endianness, mac_address = 0x10e2d5000001,
hw_mac = etherbone_mac_address) data_width = 8,
interface = "hybrid",
endianness = self.cpu.endianness)
# Software Interface. ## Software Interface.
self.add_memory_region("ethmac", getattr(self.mem_map, "ethmac", None), 0x2000, type="io") ethmac = self.get_module("ethcore_etherbone").mac
self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) ethmac_region_size = (ethmac.rx_slots.constant + ethmac.tx_slots.constant)*ethmac.slot_size.constant
ethmac_region = SoCRegion(origin=self.mem_map.get("ethmac", None), size=ethmac_region_size, cached=False)
self.bus.add_slave(name="ethmac", slave=ethmac.bus, region=ethmac_region)
# Add IRQs (if enabled).
if self.irq.enabled: if self.irq.enabled:
self.irq.add("ethmac", use_loc_if_exists=True) self.irq.add("ethmac", use_loc_if_exists=True)
# Hardware Interface.
self.arp = LiteEthARP(self.ethmac, etherbone_mac_address, etherbone_ip_address, sys_clk_freq, dw=8)
self.ip = LiteEthIP(self.ethmac, etherbone_mac_address, etherbone_ip_address, self.arp.table, dw=8)
self.icmp = LiteEthICMP(self.ip, etherbone_ip_address, dw=8)
self.udp = LiteEthUDP(self.ip, etherbone_ip_address, dw=8)
self.add_constant("ETH_PHY_NO_RESET") # Disable reset from BIOS to avoid disabling Hardware Interface. self.add_constant("ETH_PHY_NO_RESET") # Disable reset from BIOS to avoid disabling Hardware Interface.
# Etherbone
self.etherbone = LiteEthEtherbone(self.udp, 1234, mode="master")
self.bus.add_master(master=self.etherbone.wishbone.bus)
# Timing constraints
eth_rx_clk = self.ethphy.crg.cd_eth_rx.clk
eth_tx_clk = self.ethphy.crg.cd_eth_tx.clk
self.platform.add_period_constraint(eth_rx_clk, 1e9/self.ethphy.rx_clk_freq)
self.platform.add_period_constraint(eth_tx_clk, 1e9/self.ethphy.tx_clk_freq)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk)
# Video ------------------------------------------------------------------------------------ # Video ------------------------------------------------------------------------------------
video_timings = ("800x480@60Hz", { video_timings = ("800x480@60Hz", {
"pix_clk" : 33.3e6, "pix_clk" : 33.3e6,