targets: Use new HyperRAM's sys_clk_freq parameter.

litex_boards/targets/antmicro_datacenter_ddr4_test_board.py

@@ -104,7 +104,7 @@ class BaseSoC(SoCCore):
 
         # HyperRAM ---------------------------------------------------------------------------------
         if with_hyperram:
-            self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
+            self.submodules.hyperram = HyperRAM(platform.request("hyperram"), sys_clk_freq=sys_clk_freq)
             self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8*1024*1024))
 
         # SD Card ----------------------------------------------------------------------------------

litex_boards/targets/antmicro_lpddr4_test_board.py

@@ -72,7 +72,7 @@ class BaseSoC(SoCCore):
 
         # HyperRAM ---------------------------------------------------------------------------------
         if with_hyperram:
-            self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
+            self.submodules.hyperram = HyperRAM(platform.request("hyperram"), sys_clk_freq=sys_clk_freq)
             self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8*1024*1024))
 
         # SD Card ----------------------------------------------------------------------------------

litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py

@@ -62,7 +62,7 @@ class BaseSoC(SoCCore):
 
         # HyperRAM ---------------------------------------------------------------------------------
         if with_hyperram:
-            self.submodules.hyperram = HyperRAM(platform.request("hyperram"), latency=7)
+            self.submodules.hyperram = HyperRAM(platform.request("hyperram"), latency=7, sys_clk_freq=sys_clk_freq)
             self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=0x40000000, size=32*1024*1024))
 
 # Build --------------------------------------------------------------------------------------------

litex_boards/targets/lattice_crosslink_nx_vip.py

@@ -87,7 +87,7 @@ class BaseSoC(SoCCore):
             # Use HyperRAM generic PHY as SRAM -----------------------------------------------------
             size = 8*1024*kB
             hr_pads = platform.request("hyperram", int(hyperram))
-            self.submodules.hyperram = HyperRAM(hr_pads)
+            self.submodules.hyperram = HyperRAM(hr_pads, sys_clk_freq=sys_clk_freq)
             self.bus.add_slave("sram", slave=self.hyperram.bus, region=SoCRegion(size=size))
 
         # Leds -------------------------------------------------------------------------------------

litex_boards/targets/sipeed_tang_nano_4k.py

@@ -117,7 +117,7 @@ class BaseSoC(SoCCore):
             hyperram_pads = HyperRAMPads()
             self.comb += platform.request("O_hpram_ck").eq(hyperram_pads.clk)
             self.comb += platform.request("O_hpram_ck_n").eq(~hyperram_pads.clk)
-            self.submodules.hyperram = HyperRAM(hyperram_pads)
+            self.submodules.hyperram = HyperRAM(hyperram_pads, sys_clk_freq=sys_clk_freq)
             self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=0x40000000, size=8*mB))
 
         # Video ------------------------------------------------------------------------------------

litex_boards/targets/sipeed_tang_nano_9k.py

@@ -92,7 +92,7 @@ class BaseSoC(SoCCore):
             hyperram_pads = HyperRAMPads(0)
             self.comb += ck[0].eq(hyperram_pads.clk)
             self.comb += ck_n[0].eq(~hyperram_pads.clk)
-            self.submodules.hyperram = HyperRAM(hyperram_pads)
+            self.submodules.hyperram = HyperRAM(hyperram_pads, sys_clk_freq=sys_clk_freq)
             self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=self.mem_map["main_ram"], size=4*mB))
 
         # Leds -------------------------------------------------------------------------------------

litex_boards/targets/trenz_c10lprefkit.py

@@ -67,7 +67,7 @@ class BaseSoC(SoCCore):
         SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on C10 LP RefKit", **kwargs)
 
         # HyperRam ---------------------------------------------------------------------------------
-        self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
+        self.submodules.hyperram = HyperRAM(platform.request("hyperram"), sys_clk_freq=sys_clk_freq)
         self.add_wb_slave(self.mem_map["hyperram"], self.hyperram.bus)
         self.add_memory_region("hyperram", self.mem_map["hyperram"], 8*1024*1024)
 

litex_boards/targets/trenz_te0725.py

@@ -46,7 +46,7 @@ class BaseSoC(SoCCore):
         # Use HyperRAM generic PHY as SRAM ---------------------------------------------------------
         size = int((64*1024*1024) / 8)
         hr_pads = platform.request("hyperram", 0)
-        self.submodules.hyperram = HyperRAM(hr_pads)
+        self.submodules.hyperram = HyperRAM(hr_pads, sys_clk_freq=sys_clk_freq)
         self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=size))
 
         # Leds -------------------------------------------------------------------------------------