targets: Use new HyperRAM's sys_clk_freq parameter.

This commit is contained in:
Florent Kermarrec 2022-05-02 16:43:52 +02:00
parent 1e7c005480
commit 28da4f83eb
8 changed files with 8 additions and 8 deletions

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@ -104,7 +104,7 @@ class BaseSoC(SoCCore):
# HyperRAM --------------------------------------------------------------------------------- # HyperRAM ---------------------------------------------------------------------------------
if with_hyperram: if with_hyperram:
self.submodules.hyperram = HyperRAM(platform.request("hyperram")) self.submodules.hyperram = HyperRAM(platform.request("hyperram"), sys_clk_freq=sys_clk_freq)
self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8*1024*1024)) self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8*1024*1024))
# SD Card ---------------------------------------------------------------------------------- # SD Card ----------------------------------------------------------------------------------

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@ -72,7 +72,7 @@ class BaseSoC(SoCCore):
# HyperRAM --------------------------------------------------------------------------------- # HyperRAM ---------------------------------------------------------------------------------
if with_hyperram: if with_hyperram:
self.submodules.hyperram = HyperRAM(platform.request("hyperram")) self.submodules.hyperram = HyperRAM(platform.request("hyperram"), sys_clk_freq=sys_clk_freq)
self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8*1024*1024)) self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8*1024*1024))
# SD Card ---------------------------------------------------------------------------------- # SD Card ----------------------------------------------------------------------------------

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@ -62,7 +62,7 @@ class BaseSoC(SoCCore):
# HyperRAM --------------------------------------------------------------------------------- # HyperRAM ---------------------------------------------------------------------------------
if with_hyperram: if with_hyperram:
self.submodules.hyperram = HyperRAM(platform.request("hyperram"), latency=7) self.submodules.hyperram = HyperRAM(platform.request("hyperram"), latency=7, sys_clk_freq=sys_clk_freq)
self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=0x40000000, size=32*1024*1024)) self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=0x40000000, size=32*1024*1024))
# Build -------------------------------------------------------------------------------------------- # Build --------------------------------------------------------------------------------------------

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@ -87,7 +87,7 @@ class BaseSoC(SoCCore):
# Use HyperRAM generic PHY as SRAM ----------------------------------------------------- # Use HyperRAM generic PHY as SRAM -----------------------------------------------------
size = 8*1024*kB size = 8*1024*kB
hr_pads = platform.request("hyperram", int(hyperram)) hr_pads = platform.request("hyperram", int(hyperram))
self.submodules.hyperram = HyperRAM(hr_pads) self.submodules.hyperram = HyperRAM(hr_pads, sys_clk_freq=sys_clk_freq)
self.bus.add_slave("sram", slave=self.hyperram.bus, region=SoCRegion(size=size)) self.bus.add_slave("sram", slave=self.hyperram.bus, region=SoCRegion(size=size))
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------

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@ -117,7 +117,7 @@ class BaseSoC(SoCCore):
hyperram_pads = HyperRAMPads() hyperram_pads = HyperRAMPads()
self.comb += platform.request("O_hpram_ck").eq(hyperram_pads.clk) self.comb += platform.request("O_hpram_ck").eq(hyperram_pads.clk)
self.comb += platform.request("O_hpram_ck_n").eq(~hyperram_pads.clk) self.comb += platform.request("O_hpram_ck_n").eq(~hyperram_pads.clk)
self.submodules.hyperram = HyperRAM(hyperram_pads) self.submodules.hyperram = HyperRAM(hyperram_pads, sys_clk_freq=sys_clk_freq)
self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=0x40000000, size=8*mB)) self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=0x40000000, size=8*mB))
# Video ------------------------------------------------------------------------------------ # Video ------------------------------------------------------------------------------------

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@ -92,7 +92,7 @@ class BaseSoC(SoCCore):
hyperram_pads = HyperRAMPads(0) hyperram_pads = HyperRAMPads(0)
self.comb += ck[0].eq(hyperram_pads.clk) self.comb += ck[0].eq(hyperram_pads.clk)
self.comb += ck_n[0].eq(~hyperram_pads.clk) self.comb += ck_n[0].eq(~hyperram_pads.clk)
self.submodules.hyperram = HyperRAM(hyperram_pads) self.submodules.hyperram = HyperRAM(hyperram_pads, sys_clk_freq=sys_clk_freq)
self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=self.mem_map["main_ram"], size=4*mB)) self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=self.mem_map["main_ram"], size=4*mB))
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------

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@ -67,7 +67,7 @@ class BaseSoC(SoCCore):
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on C10 LP RefKit", **kwargs) SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on C10 LP RefKit", **kwargs)
# HyperRam --------------------------------------------------------------------------------- # HyperRam ---------------------------------------------------------------------------------
self.submodules.hyperram = HyperRAM(platform.request("hyperram")) self.submodules.hyperram = HyperRAM(platform.request("hyperram"), sys_clk_freq=sys_clk_freq)
self.add_wb_slave(self.mem_map["hyperram"], self.hyperram.bus) self.add_wb_slave(self.mem_map["hyperram"], self.hyperram.bus)
self.add_memory_region("hyperram", self.mem_map["hyperram"], 8*1024*1024) self.add_memory_region("hyperram", self.mem_map["hyperram"], 8*1024*1024)

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@ -46,7 +46,7 @@ class BaseSoC(SoCCore):
# Use HyperRAM generic PHY as SRAM --------------------------------------------------------- # Use HyperRAM generic PHY as SRAM ---------------------------------------------------------
size = int((64*1024*1024) / 8) size = int((64*1024*1024) / 8)
hr_pads = platform.request("hyperram", 0) hr_pads = platform.request("hyperram", 0)
self.submodules.hyperram = HyperRAM(hr_pads) self.submodules.hyperram = HyperRAM(hr_pads, sys_clk_freq=sys_clk_freq)
self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=size)) self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=size))
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------