targets: Use new HyperRAM's sys_clk_freq parameter.
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@ -104,7 +104,7 @@ class BaseSoC(SoCCore):
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# HyperRAM ---------------------------------------------------------------------------------
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# HyperRAM ---------------------------------------------------------------------------------
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if with_hyperram:
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if with_hyperram:
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self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
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self.submodules.hyperram = HyperRAM(platform.request("hyperram"), sys_clk_freq=sys_clk_freq)
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self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8*1024*1024))
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self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8*1024*1024))
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# SD Card ----------------------------------------------------------------------------------
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# SD Card ----------------------------------------------------------------------------------
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@ -72,7 +72,7 @@ class BaseSoC(SoCCore):
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# HyperRAM ---------------------------------------------------------------------------------
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# HyperRAM ---------------------------------------------------------------------------------
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if with_hyperram:
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if with_hyperram:
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self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
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self.submodules.hyperram = HyperRAM(platform.request("hyperram"), sys_clk_freq=sys_clk_freq)
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self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8*1024*1024))
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self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8*1024*1024))
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# SD Card ----------------------------------------------------------------------------------
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# SD Card ----------------------------------------------------------------------------------
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@ -62,7 +62,7 @@ class BaseSoC(SoCCore):
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# HyperRAM ---------------------------------------------------------------------------------
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# HyperRAM ---------------------------------------------------------------------------------
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if with_hyperram:
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if with_hyperram:
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self.submodules.hyperram = HyperRAM(platform.request("hyperram"), latency=7)
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self.submodules.hyperram = HyperRAM(platform.request("hyperram"), latency=7, sys_clk_freq=sys_clk_freq)
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self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=0x40000000, size=32*1024*1024))
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self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=0x40000000, size=32*1024*1024))
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# Build --------------------------------------------------------------------------------------------
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# Build --------------------------------------------------------------------------------------------
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@ -87,7 +87,7 @@ class BaseSoC(SoCCore):
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# Use HyperRAM generic PHY as SRAM -----------------------------------------------------
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# Use HyperRAM generic PHY as SRAM -----------------------------------------------------
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size = 8*1024*kB
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size = 8*1024*kB
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hr_pads = platform.request("hyperram", int(hyperram))
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hr_pads = platform.request("hyperram", int(hyperram))
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self.submodules.hyperram = HyperRAM(hr_pads)
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self.submodules.hyperram = HyperRAM(hr_pads, sys_clk_freq=sys_clk_freq)
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self.bus.add_slave("sram", slave=self.hyperram.bus, region=SoCRegion(size=size))
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self.bus.add_slave("sram", slave=self.hyperram.bus, region=SoCRegion(size=size))
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# Leds -------------------------------------------------------------------------------------
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# Leds -------------------------------------------------------------------------------------
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@ -117,7 +117,7 @@ class BaseSoC(SoCCore):
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hyperram_pads = HyperRAMPads()
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hyperram_pads = HyperRAMPads()
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self.comb += platform.request("O_hpram_ck").eq(hyperram_pads.clk)
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self.comb += platform.request("O_hpram_ck").eq(hyperram_pads.clk)
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self.comb += platform.request("O_hpram_ck_n").eq(~hyperram_pads.clk)
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self.comb += platform.request("O_hpram_ck_n").eq(~hyperram_pads.clk)
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self.submodules.hyperram = HyperRAM(hyperram_pads)
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self.submodules.hyperram = HyperRAM(hyperram_pads, sys_clk_freq=sys_clk_freq)
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self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=0x40000000, size=8*mB))
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self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=0x40000000, size=8*mB))
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# Video ------------------------------------------------------------------------------------
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# Video ------------------------------------------------------------------------------------
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@ -92,7 +92,7 @@ class BaseSoC(SoCCore):
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hyperram_pads = HyperRAMPads(0)
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hyperram_pads = HyperRAMPads(0)
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self.comb += ck[0].eq(hyperram_pads.clk)
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self.comb += ck[0].eq(hyperram_pads.clk)
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self.comb += ck_n[0].eq(~hyperram_pads.clk)
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self.comb += ck_n[0].eq(~hyperram_pads.clk)
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self.submodules.hyperram = HyperRAM(hyperram_pads)
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self.submodules.hyperram = HyperRAM(hyperram_pads, sys_clk_freq=sys_clk_freq)
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self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=self.mem_map["main_ram"], size=4*mB))
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self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=self.mem_map["main_ram"], size=4*mB))
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# Leds -------------------------------------------------------------------------------------
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# Leds -------------------------------------------------------------------------------------
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@ -67,7 +67,7 @@ class BaseSoC(SoCCore):
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on C10 LP RefKit", **kwargs)
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on C10 LP RefKit", **kwargs)
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# HyperRam ---------------------------------------------------------------------------------
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# HyperRam ---------------------------------------------------------------------------------
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self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
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self.submodules.hyperram = HyperRAM(platform.request("hyperram"), sys_clk_freq=sys_clk_freq)
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self.add_wb_slave(self.mem_map["hyperram"], self.hyperram.bus)
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self.add_wb_slave(self.mem_map["hyperram"], self.hyperram.bus)
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self.add_memory_region("hyperram", self.mem_map["hyperram"], 8*1024*1024)
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self.add_memory_region("hyperram", self.mem_map["hyperram"], 8*1024*1024)
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@ -46,7 +46,7 @@ class BaseSoC(SoCCore):
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# Use HyperRAM generic PHY as SRAM ---------------------------------------------------------
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# Use HyperRAM generic PHY as SRAM ---------------------------------------------------------
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size = int((64*1024*1024) / 8)
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size = int((64*1024*1024) / 8)
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hr_pads = platform.request("hyperram", 0)
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hr_pads = platform.request("hyperram", 0)
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self.submodules.hyperram = HyperRAM(hr_pads)
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self.submodules.hyperram = HyperRAM(hr_pads, sys_clk_freq=sys_clk_freq)
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self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=size))
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self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=size))
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# Leds -------------------------------------------------------------------------------------
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# Leds -------------------------------------------------------------------------------------
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