Chen
GitHub
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Fei Gao <feig@princeton.edu>
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2022 Jiajie Chen <c@jia.je>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxUSPPlatform, VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk100_ddr4", 0,
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Subsignal("p", Pins("BH51"), IOStandard("LVDS")),
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Subsignal("n", Pins("BJ51"), IOStandard("LVDS")),
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),
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("clk100_qdr4", 0,
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Subsignal("p", Pins("BJ4"), IOStandard("LVDS")),
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Subsignal("n", Pins("BK3"), IOStandard("LVDS")),
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),
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("clk100_rld3", 0,
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Subsignal("p", Pins("F35"), IOStandard("LVDS")),
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Subsignal("n", Pins("F36"), IOStandard("LVDS")),
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),
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("cpu_reset", 0, Pins("BM29"), IOStandard("LVCMOS12")),
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# Leds
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("user_led", 0, Pins("BH24"), IOStandard("LVCMOS18")),
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("user_led", 1, Pins("BG24"), IOStandard("LVCMOS18")),
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("user_led", 2, Pins("BG25"), IOStandard("LVCMOS18")),
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("user_led", 3, Pins("BF25"), IOStandard("LVCMOS18")),
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("user_led", 4, Pins("BF26"), IOStandard("LVCMOS18")),
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("user_led", 5, Pins("BF27"), IOStandard("LVCMOS18")),
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("user_led", 6, Pins("BG27"), IOStandard("LVCMOS18")),
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("user_led", 7, Pins("BG28"), IOStandard("LVCMOS18")),
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# Serial
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("serial", 0,
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Subsignal("rx", Pins("BP26"), IOStandard("LVCMOS18")),
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Subsignal("rts", Pins("BP22"), IOStandard("LVCMOS18")),
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Subsignal("tx", Pins("BN26"), IOStandard("LVCMOS18")),
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Subsignal("cts", Pins("BP23"), IOStandard("LVCMOS18")),
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),
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("serial", 1,
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Subsignal("rx", Pins("BK28"), IOStandard("LVCMOS18")),
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Subsignal("rts", Pins("BL26"), IOStandard("LVCMOS18")),
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Subsignal("tx", Pins("BJ28"), IOStandard("LVCMOS18")),
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Subsignal("cts", Pins("BL27"), IOStandard("LVCMOS18")),
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),
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# DDR4 memory
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("ddram", 0,
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Subsignal("a", Pins(
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"BF50 BD51 BG48 BE50 BE49 BE51 BF53 BG50",
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"BF51 BG47 BF47 BG49 BF48 BF52"),
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IOStandard("SSTL12_DCI")),
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Subsignal("ba", Pins("BE54 BE53"), IOStandard("SSTL12_DCI")),
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Subsignal("bg", Pins("BG54"), IOStandard("SSTL12_DCI")),
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Subsignal("ras_n", Pins("BJ54"), IOStandard("SSTL12_DCI")),
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Subsignal("cas_n", Pins("BH54"), IOStandard("SSTL12_DCI")),
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Subsignal("we_n", Pins("BG53"), IOStandard("SSTL12_DCI")),
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Subsignal("cs_n", Pins("BP49 BK48"), IOStandard("SSTL12_DCI")), # Clam-shell topology
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Subsignal("act_n", Pins("BG52"), IOStandard("SSTL12_DCI")),
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#Subsignal("ten", Pins("BJ53"), IOStandard("SSTL12_DCI")),
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#Subsignal("alert_n", Pins("BJ52"), IOStandard("SSTL12_DCI")),
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#Subsignal("par", Pins("BL48"), IOStandard("SSTL12_DCI")),
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Subsignal("dm", Pins(
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"BN42 BL47 BH42 BD41 BM28 BM34 BH32 BG29"),
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IOStandard("POD12_DCI")),
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Subsignal("dq", Pins(
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"BM45 BP44 BP47 BN45 BM44 BN44 BN47 BP43",
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"BL45 BK44 BL46 BK43 BL43 BJ44 BL42 BJ43",
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"BK41 BG44 BG42 BH44 BH45 BG45 BG43 BJ41",
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"BE43 BF42 BC42 BF43 BD42 BF45 BE44 BF46",
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"BP32 BP29 BP31 BP28 BN32 BM30 BN31 BL30",
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"BL32 BP34 BN34 BK33 BL31 BL33 BM33 BK31",
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"BJ34 BG35 BH34 BH35 BJ33 BF35 BG34 BF36",
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"BF31 BH30 BJ31 BG32 BH31 BF32 BH29 BF33"),
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IOStandard("POD12_DCI"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("dqs_p", Pins("BN46 BK45 BH46 BE45 BN29 BL35 BK34 BJ29"),
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IOStandard("DIFF_POD12"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("dqs_n", Pins("BP46 BK46 BJ46 BE46 BN30 BM35 BK35 BK30"),
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IOStandard("DIFF_POD12"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("clk_p", Pins("BK53"), IOStandard("DIFF_SSTL12_DCI")),
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Subsignal("clk_n", Pins("BK54"), IOStandard("DIFF_SSTL12_DCI")),
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Subsignal("cke", Pins("BH52"), IOStandard("SSTL12_DCI")),
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Subsignal("odt", Pins("BH49"), IOStandard("SSTL12_DCI")),
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Subsignal("reset_n", Pins("BH50"), IOStandard("LVCMOS12")),
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Misc("SLEW=FAST"),
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),
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# SGMII Clock
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("eth_clocks", 0,
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Subsignal("p", Pins("BH27"), IOStandard("LVDS")),
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Subsignal("n", Pins("BJ27"), IOStandard("LVDS")),
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),
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# SGMII Ethernet
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("eth", 0,
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Subsignal("int_n", Pins("BF22"), IOStandard("LVCMOS18")),
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Subsignal("mdio", Pins("BG23"), IOStandard("LVCMOS18")),
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Subsignal("mdc", Pins("BN27"), IOStandard("LVCMOS18")),
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Subsignal("rx_p", Pins("BJ22"), IOStandard("LVDS")),
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Subsignal("rx_n", Pins("BK21"), IOStandard("LVDS")),
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Subsignal("tx_p", Pins("BG22"), IOStandard("LVDS")),
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Subsignal("tx_n", Pins("BH22"), IOStandard("LVDS")),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = []
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxUSPPlatform):
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default_clk_name = "clk100_ddr4"
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default_clk_period = 1e9/100e6
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def __init__(self, toolchain="vivado"):
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XilinxUSPPlatform.__init__(self, "xcvu37p-fsvh2892-2L-e", _io, _connectors, toolchain="vivado")
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def create_programmer(self):
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return VivadoProgrammer()
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def do_finalize(self, fragment):
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XilinxUSPPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk100_ddr4", loose=True), 1e9/100e6)
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self.add_period_constraint(self.lookup_request("clk100_qdr4", loose=True), 1e9/100e6)
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self.add_period_constraint(self.lookup_request("clk100_rld3", loose=True), 1e9/100e6)
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# DDR4 memory Internal Vref
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self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 64]")
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self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 65]")
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self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 66]")
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# For HBM2 IP in Vivado 2019.2 (https://www.xilinx.com/support/answers/72607.html)
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self.add_platform_command("connect_debug_port dbg_hub/clk [get_nets apb_clk]")
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@ -0,0 +1,142 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Fei Gao <feig@princeton.edu>
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2022 Jiajie Chen <c@jia.je>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.gen import *
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from litex_boards.platforms import xilinx_vcu128
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from litex.soc.cores.clock import *
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from litex.soc.cores.ram.xilinx_usp_hbm2 import USPHBM2
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from litex.soc.interconnect.axi import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT40A512M16
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from litedram.phy import usddrphy
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, with_hbm):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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if with_hbm:
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self.cd_hbm_ref = ClockDomain()
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self.cd_apb = ClockDomain()
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else: # DDR4
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self.cd_sys4x = ClockDomain()
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self.cd_pll4x = ClockDomain()
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self.cd_idelay = ClockDomain()
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# # #
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self.pll = pll = USMMCM(speedgrade=-2)
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self.comb += pll.reset.eq(platform.request("cpu_reset") | self.rst)
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pll.register_clkin(platform.request("clk100_ddr4"), 100e6)
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if with_hbm:
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_hbm_ref, 100e6)
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pll.create_clkout(self.cd_apb, 100e6)
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platform.add_false_path_constraints(self.cd_sys.clk, self.cd_apb.clk)
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else:
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pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
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pll.create_clkout(self.cd_idelay, 500e6)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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self.specials += [
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Instance("BUFGCE_DIV",
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p_BUFGCE_DIVIDE=4,
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i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
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Instance("BUFGCE",
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i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
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]
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self.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_idelay, cd_sys=self.cd_sys)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=125e6, with_led_chaser=True, with_hbm=False, **kwargs):
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platform = xilinx_vcu128.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq, with_hbm)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on VCU128", **kwargs)
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# HBM --------------------------------------------------------------------------------------
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if with_hbm:
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# Add HBM Core.
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self.hbm = hbm = ClockDomainsRenamer({"axi": "sys"})(USPHBM2(platform))
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# Get HBM .xci.
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os.system("wget https://github.com/litex-hub/litex-boards/files/6893157/hbm_0.xci.txt")
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os.makedirs("ip/hbm", exist_ok=True)
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os.system("mv hbm_0.xci.txt ip/hbm/hbm_0.xci")
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# Connect four of the HBM's AXI interfaces to the main bus of the SoC.
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for i in range(4):
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axi_hbm = hbm.axi[i]
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axi_lite_hbm = AXILiteInterface(data_width=256, address_width=33)
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self.submodules += AXILite2AXI(axi_lite_hbm, axi_hbm)
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self.bus.add_slave(f"hbm{i}", axi_lite_hbm, SoCRegion(origin=0x4000_0000 + 0x1000_0000*i, size=0x1000_0000)) # 256MB.
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# Link HBM2 channel 0 as main RAM
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self.bus.add_region("main_ram", SoCRegion(origin=0x4000_0000, size=0x1000_0000, linker=True)) # 256MB.
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elif not self.integrated_main_ram_size:
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# DDR4 SDRAM -------------------------------------------------------------------------------
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self.ddrphy = usddrphy.USPDDRPHY(
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pads = platform.request("ddram"),
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memtype = "DDR4",
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sys_clk_freq = sys_clk_freq,
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is_clam_shell = True,
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iodelay_clk_freq = 500e6)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT40A512M16(sys_clk_freq, "1:4"),
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size = 0x40000000,
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=xilinx_vcu128.Platform, description="LiteX SoC on VCU128.")
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parser.add_target_argument("--sys-clk-freq", default=125e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--with-hbm", action="store_true", help="Use HBM2.")
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = args.sys_clk_freq,
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with_hbm = args.with_hbm,
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**parser.soc_argdict
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)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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