mirror of
https://github.com/litex-hub/litex-boards.git
synced 2025-01-03 03:43:36 -05:00
platforms/pipistrello: cleanup, remove extra stuff specific to litex-buildenv
This commit is contained in:
Florent Kermarrec
parent
c96e7c8fb9
commit
2b43a18a3c
1 changed files with 85 additions and 129 deletions
|
|
@ -3,8 +3,12 @@
|
|||
# This file is Copyright (c) 2015 Robert Jordens <jordens@gmail.com>
|
||||
# This file is Copyright (c) 2015 Sebastien Bourdeauducq <sb@m-labs.hk>
|
||||
# This file is Copyright (c) 2015 Yann Sionneau <yann.sionneau@gmail.com>
|
||||
# This file is Copyright (c) 2016-2017 Tim 'mithro' Ansell <mithro@mithis.com>
|
||||
# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
|
||||
# License: BSD
|
||||
|
||||
import argparse
|
||||
|
||||
from fractions import Fraction
|
||||
|
||||
from migen import *
|
||||
|
|
@ -17,55 +21,45 @@ from litex.soc.integration.builder import *
|
|||
|
||||
from litedram.modules import MT46H32M16
|
||||
from litedram.phy import s6ddrphy
|
||||
from litedram.core import ControllerSettings
|
||||
|
||||
|
||||
import argparse
|
||||
|
||||
# CRG ----------------------------------------------------------------------------------------------
|
||||
|
||||
class _CRG(Module):
|
||||
def __init__(self, platform, clk_freq):
|
||||
# Clock domains for the system (soft CPU and related components run at).
|
||||
self.clock_domains.cd_sys = ClockDomain()
|
||||
# Clock domains for the DDR interface.
|
||||
self.clock_domains.cd_sdram_half = ClockDomain()
|
||||
def __init__(self, platform, sys_clk_freq):
|
||||
self.clock_domains.cd_sys = ClockDomain()
|
||||
self.clock_domains.cd_sdram_half = ClockDomain()
|
||||
self.clock_domains.cd_sdram_full_wr = ClockDomain()
|
||||
self.clock_domains.cd_sdram_full_rd = ClockDomain()
|
||||
# Clock domain for peripherals (such as HDMI output).
|
||||
self.clock_domains.cd_base50 = ClockDomain()
|
||||
|
||||
self.reset = Signal()
|
||||
|
||||
# Input 50MHz clock
|
||||
f0 = 50*1000000
|
||||
clk50 = platform.request("clk50")
|
||||
clk50a = Signal()
|
||||
# Input 50MHz clock (buffered)
|
||||
#self.specials += Instance("IBUFG", i_I=clk50, o_O=clk50a)
|
||||
clk50b = Signal()
|
||||
self.specials += Instance(
|
||||
"BUFIO2", p_DIVIDE=1,
|
||||
p_DIVIDE_BYPASS="TRUE", p_I_INVERT="FALSE",
|
||||
# # #
|
||||
|
||||
# Input clock ------------------------------------------------------------------------------
|
||||
clk50_freq = int(50e6)
|
||||
clk50 = platform.request("clk50")
|
||||
clk50b = Signal()
|
||||
self.specials += Instance("BUFIO2",
|
||||
p_DIVIDE=1, p_DIVIDE_BYPASS="TRUE",
|
||||
p_I_INVERT="FALSE",
|
||||
i_I=clk50, o_DIVCLK=clk50b)
|
||||
|
||||
# PLL --------------------------------------------------------------------------------------
|
||||
pll_lckd = Signal()
|
||||
pll_fb = Signal()
|
||||
pll_sdram_full = Signal()
|
||||
pll_sdram_half_a = Signal()
|
||||
pll_sdram_half_b = Signal()
|
||||
pll_unused = Signal()
|
||||
pll_sys = Signal()
|
||||
pll_periph = Signal()
|
||||
|
||||
p = 12
|
||||
f = Fraction(clk_freq*p, f0)
|
||||
f = Fraction(sys_clk_freq*p, clk50_freq)
|
||||
n, d = f.numerator, f.denominator
|
||||
assert 19e6 <= f0/d <= 500e6 # pfd
|
||||
assert 400e6 <= f0*n/d <= 1080e6 # vco
|
||||
assert 19e6 <= clk50_freq/d <= 500e6 # pfd
|
||||
assert 400e6 <= clk50_freq*n/d <= 1080e6 # vco
|
||||
|
||||
# Unbuffered output signals from the PLL. They need to be buffered
|
||||
# before feeding into the fabric.
|
||||
unbuf_sdram_full = Signal()
|
||||
unbuf_sdram_half_a = Signal()
|
||||
unbuf_sdram_half_b = Signal()
|
||||
unbuf_unused = Signal()
|
||||
unbuf_sys = Signal()
|
||||
unbuf_periph = Signal()
|
||||
|
||||
# PLL signals
|
||||
pll_lckd = Signal()
|
||||
pll_fb = Signal()
|
||||
self.specials.pll = Instance(
|
||||
"PLL_ADV",
|
||||
name="crg_pll_adv",
|
||||
|
|
@ -75,7 +69,7 @@ class _CRG(Module):
|
|||
p_DIVCLK_DIVIDE=d,
|
||||
# Input Clocks (50MHz)
|
||||
i_CLKIN1=clk50b,
|
||||
p_CLKIN1_PERIOD=1e9/f0,
|
||||
p_CLKIN1_PERIOD=1e9/clk50_freq,
|
||||
i_CLKIN2=0,
|
||||
p_CLKIN2_PERIOD=0.,
|
||||
i_CLKINSEL=1,
|
||||
|
|
@ -84,142 +78,104 @@ class _CRG(Module):
|
|||
p_CLK_FEEDBACK="CLKFBOUT",
|
||||
p_CLKFBOUT_MULT=n, p_CLKFBOUT_PHASE=0.,
|
||||
# (333MHz) sdram wr rd
|
||||
o_CLKOUT0=unbuf_sdram_full, p_CLKOUT0_DUTY_CYCLE=.5,
|
||||
o_CLKOUT0=pll_sdram_full, p_CLKOUT0_DUTY_CYCLE=.5,
|
||||
p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=p//4,
|
||||
# unused?
|
||||
o_CLKOUT1=unbuf_unused, p_CLKOUT1_DUTY_CYCLE=.5,
|
||||
o_CLKOUT1=pll_unused, p_CLKOUT1_DUTY_CYCLE=.5,
|
||||
p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=15,
|
||||
# (166MHz) sdram_half - sdram dqs adr ctrl
|
||||
o_CLKOUT2=unbuf_sdram_half_a, p_CLKOUT2_DUTY_CYCLE=.5,
|
||||
o_CLKOUT2=pll_sdram_half_a, p_CLKOUT2_DUTY_CYCLE=.5,
|
||||
p_CLKOUT2_PHASE=270., p_CLKOUT2_DIVIDE=p//2,
|
||||
# (166MHz) off-chip ddr
|
||||
o_CLKOUT3=unbuf_sdram_half_b, p_CLKOUT3_DUTY_CYCLE=.5,
|
||||
o_CLKOUT3=pll_sdram_half_b, p_CLKOUT3_DUTY_CYCLE=.5,
|
||||
p_CLKOUT3_PHASE=250., p_CLKOUT3_DIVIDE=p//2,
|
||||
# ( 50MHz) periph
|
||||
o_CLKOUT4=unbuf_periph, p_CLKOUT4_DUTY_CYCLE=.5,
|
||||
o_CLKOUT4=pll_periph, p_CLKOUT4_DUTY_CYCLE=.5,
|
||||
p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=20,
|
||||
# ( 83MHz) sysclk
|
||||
o_CLKOUT5=unbuf_sys, p_CLKOUT5_DUTY_CYCLE=.5,
|
||||
o_CLKOUT5=pll_sys, p_CLKOUT5_DUTY_CYCLE=.5,
|
||||
p_CLKOUT5_PHASE=0., p_CLKOUT5_DIVIDE=p//1,
|
||||
)
|
||||
|
||||
|
||||
# power on reset?
|
||||
# Power on reset
|
||||
reset = platform.request("user_btn") | self.reset
|
||||
self.clock_domains.cd_por = ClockDomain()
|
||||
por = Signal(max=1 << 11, reset=(1 << 11) - 1)
|
||||
self.sync.por += If(por != 0, por.eq(por - 1))
|
||||
self.specials += AsyncResetSynchronizer(self.cd_por, reset)
|
||||
|
||||
# System clock - 83MHz
|
||||
self.specials += Instance("BUFG", i_I=unbuf_sys, o_O=self.cd_sys.clk)
|
||||
# System clock
|
||||
self.specials += Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk)
|
||||
self.comb += self.cd_por.clk.eq(self.cd_sys.clk)
|
||||
self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd | (por > 0))
|
||||
|
||||
|
||||
# SDRAM clocks
|
||||
# ------------------------------------------------------------------------------
|
||||
# SDRAM clocks -----------------------------------------------------------------------------
|
||||
self.clk4x_wr_strb = Signal()
|
||||
self.clk4x_rd_strb = Signal()
|
||||
|
||||
# sdram_full
|
||||
# SDRAM full clock
|
||||
self.specials += Instance("BUFPLL", name="sdram_full_bufpll",
|
||||
p_DIVIDE=4,
|
||||
i_PLLIN=unbuf_sdram_full, i_GCLK=self.cd_sys.clk,
|
||||
i_LOCKED=pll_lckd,
|
||||
o_IOCLK=self.cd_sdram_full_wr.clk,
|
||||
o_SERDESSTROBE=self.clk4x_wr_strb)
|
||||
p_DIVIDE = 4,
|
||||
i_PLLIN = pll_sdram_full, i_GCLK=self.cd_sys.clk,
|
||||
i_LOCKED = pll_lckd,
|
||||
o_IOCLK = self.cd_sdram_full_wr.clk,
|
||||
o_SERDESSTROBE = self.clk4x_wr_strb)
|
||||
self.comb += [
|
||||
self.cd_sdram_full_rd.clk.eq(self.cd_sdram_full_wr.clk),
|
||||
self.clk4x_rd_strb.eq(self.clk4x_wr_strb),
|
||||
]
|
||||
# sdram_half
|
||||
self.specials += Instance("BUFG", name="sdram_half_a_bufpll", i_I=unbuf_sdram_half_a, o_O=self.cd_sdram_half.clk)
|
||||
# SDRAM_half clock
|
||||
self.specials += Instance("BUFG", name="sdram_half_a_bufpll",
|
||||
i_I=pll_sdram_half_a, o_O=self.cd_sdram_half.clk)
|
||||
clk_sdram_half_shifted = Signal()
|
||||
self.specials += Instance("BUFG", name="sdram_half_b_bufpll", i_I=unbuf_sdram_half_b, o_O=clk_sdram_half_shifted)
|
||||
self.specials += Instance("BUFG", name="sdram_half_b_bufpll",
|
||||
i_I=pll_sdram_half_b, o_O=clk_sdram_half_shifted)
|
||||
clk = platform.request("ddram_clock")
|
||||
self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE",
|
||||
p_INIT=0, p_SRTYPE="SYNC",
|
||||
i_D0=1, i_D1=0, i_S=0, i_R=0, i_CE=1,
|
||||
i_C0=clk_sdram_half_shifted,
|
||||
i_C1=~clk_sdram_half_shifted,
|
||||
o_Q=clk.p)
|
||||
p_INIT=0, p_SRTYPE="SYNC",
|
||||
i_D0=1, i_D1=0, i_S=0, i_R=0, i_CE=1,
|
||||
i_C0=clk_sdram_half_shifted,
|
||||
i_C1=~clk_sdram_half_shifted,
|
||||
o_Q=clk.p)
|
||||
self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE",
|
||||
p_INIT=0, p_SRTYPE="SYNC",
|
||||
i_D0=0, i_D1=1, i_S=0, i_R=0, i_CE=1,
|
||||
i_C0=clk_sdram_half_shifted, i_C1=~clk_sdram_half_shifted,
|
||||
o_Q=clk.n)
|
||||
|
||||
# Peripheral clock - 50MHz
|
||||
# ------------------------------------------------------------------------------
|
||||
# The peripheral clock is kept separate from the system clock to allow
|
||||
# the system clock to be increased in the future.
|
||||
dcm_base50_locked = Signal()
|
||||
self.specials += [
|
||||
Instance("DCM_CLKGEN", name="crg_periph_dcm_clkgen",
|
||||
p_CLKIN_PERIOD=20.0,
|
||||
p_CLKFX_MULTIPLY=2,
|
||||
p_CLKFX_DIVIDE=2,
|
||||
p_CLKFX_MD_MAX=1.0, # CLKFX_MULTIPLY/CLKFX_DIVIDE
|
||||
p_CLKFXDV_DIVIDE=2,
|
||||
p_SPREAD_SPECTRUM="NONE",
|
||||
p_STARTUP_WAIT="FALSE",
|
||||
|
||||
i_CLKIN=clk50a,
|
||||
o_CLKFX=self.cd_base50.clk,
|
||||
o_LOCKED=dcm_base50_locked,
|
||||
i_FREEZEDCM=0,
|
||||
i_RST=ResetSignal(),
|
||||
),
|
||||
AsyncResetSynchronizer(self.cd_base50,
|
||||
self.cd_sys.rst | ~dcm_base50_locked)
|
||||
]
|
||||
platform.add_period_constraint(self.cd_base50.clk, 20)
|
||||
p_INIT=0, p_SRTYPE="SYNC",
|
||||
i_D0=0, i_D1=1, i_S=0, i_R=0, i_CE=1,
|
||||
i_C0=clk_sdram_half_shifted,
|
||||
i_C1=~clk_sdram_half_shifted,
|
||||
o_Q=clk.n)
|
||||
|
||||
# BaseSoC ------------------------------------------------------------------------------------------
|
||||
|
||||
class BaseSoC(SoCSDRAM):
|
||||
def __init__(self, integrated_rom_size=0x8000, **kwargs):
|
||||
sys_clk_freq = (83 + Fraction(1, 3))*1000*1000
|
||||
platform = pipistrello.Platform()
|
||||
|
||||
mem_map = {
|
||||
"spiflash": 0x20000000, # (default shadow @0xa0000000)
|
||||
}
|
||||
mem_map.update(SoCSDRAM.mem_map)
|
||||
# SoCSDRAM ---------------------------------------------------------------------------------
|
||||
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
|
||||
integrated_rom_size=integrated_rom_size,
|
||||
integrated_sram_size=0x8000,
|
||||
**kwargs)
|
||||
|
||||
# CRG --------------------------------------------------------------------------------------
|
||||
self.submodules.crg = _CRG(platform, sys_clk_freq)
|
||||
self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/sys_clk_freq)
|
||||
|
||||
def __init__(self, **kwargs):
|
||||
if 'integrated_rom_size' not in kwargs:
|
||||
kwargs['integrated_rom_size']=0x8000
|
||||
if 'integrated_sram_size' not in kwargs:
|
||||
kwargs['integrated_sram_size']=0x8000
|
||||
|
||||
clk_freq = (83 + Fraction(1, 3))*1000*1000
|
||||
|
||||
platform = pipistrello.Platform()
|
||||
|
||||
SoCSDRAM.__init__(self, platform, clk_freq, **kwargs)
|
||||
|
||||
self.submodules.crg = _CRG(platform, clk_freq)
|
||||
self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/clk_freq)
|
||||
|
||||
|
||||
bios_size = 0x8000
|
||||
# sdram
|
||||
sdram_module = MT46H32M16(self.clk_freq, "1:2")
|
||||
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
|
||||
platform.request("ddram"),
|
||||
sdram_module.memtype,
|
||||
rd_bitslip=1,
|
||||
wr_bitslip=3,
|
||||
dqs_ddr_alignment="C1")
|
||||
self.add_csr("ddrphy")
|
||||
controller_settings = ControllerSettings(with_bandwidth=True)
|
||||
self.register_sdram(self.ddrphy,
|
||||
sdram_module.geom_settings,
|
||||
sdram_module.timing_settings,
|
||||
controller_settings=controller_settings)
|
||||
# LPDDR SDRAM ------------------------------------------------------------------------------
|
||||
self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(platform.request("ddram"),
|
||||
memtype = "LPDDR",
|
||||
rd_bitslip = 1,
|
||||
wr_bitslip = 3,
|
||||
dqs_ddr_alignment = "C1")
|
||||
self.comb += [
|
||||
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
|
||||
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
|
||||
]
|
||||
self.add_csr("ddrphy")
|
||||
sdram_module = MT46H32M16(sys_clk_freq, "1:2")
|
||||
self.register_sdram(self.ddrphy,
|
||||
geom_settings = sdram_module.geom_settings,
|
||||
timing_settings = sdram_module.timing_settings)
|
||||
|
||||
# Build --------------------------------------------------------------------------------------------
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue