digilent_arty_z7: Defaults to no_uart.
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@ -113,6 +113,7 @@ def main():
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soc_core_args(parser)
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vivado_build_args(parser)
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parser.set_defaults(cpu_type="zynq7000")
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parser.set_defaults(no_uart=True)
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args = parser.parse_args()
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soc = BaseSoC(
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