targets/trenz_tec0117: Switch to new GW1NPLL.
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9686db0ed3
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@ -15,6 +15,7 @@ from migen import *
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from litex.build.io import CRG
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from litex.soc.cores.clock.gowin_gw1n import GW1NPLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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@ -41,16 +42,12 @@ class _CRG(Module):
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clk100 = platform.request("clk100")
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rst_n = platform.request("rst_n")
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# Generate 25Mhz sys_clk_freq clock from 100MHz input clock, FIXME: use PLL.
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assert sys_clk_freq == 25e6
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self.clock_domains.cd_clk100 = ClockDomain()
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self.comb += self.cd_clk100.clk.eq(clk100)
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count = Signal(2)
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self.sync.clk100 += count.eq(count + 1)
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clk50 = count[0]
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clk25 = count[1]
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self.comb += self.cd_sys.clk.eq(clk25)
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self.comb += self.cd_sys.rst.eq(~rst_n | self.rst) # FIXME: use AsyncResetSynchronizer
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# PLL
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self.submodules.pll = pll = GW1NPLL(device="GW1N9K")
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self.comb += pll.reset.eq(~rst_n)
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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self.comb += self.cd_sys.rst.eq(~rst_n) # FIXME: Move to GW1NPLL and use lock.
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# BaseSoC ------------------------------------------------------------------------------------------
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@ -187,7 +184,7 @@ def main():
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--bios-flash-offset", default=0x80000, help="BIOS offset in SPI Flash (0x00000 default)")
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parser.add_argument("--flash", action="store_true", help="Flash Bitstream and BIOS")
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parser.add_argument("--sys-clk-freq", default=25e6, help="System clock frequency (default: 12MHz)")
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parser.add_argument("--sys-clk-freq", default=25e6, help="System clock frequency (default: 25MHz)")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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