pano_logic_g2: switch to LiteEthPHY and simplify Ethernet/Etherbone.
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33fe308ef0
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@ -16,7 +16,7 @@ from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from liteeth.phy import LiteEthPHYGMII
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from liteeth.phy import LiteEthPHY
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# CRG ----------------------------------------------------------------------------------------------
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@ -50,24 +50,17 @@ class BaseSoC(SoCCore):
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq, with_ethernet=with_ethernet or with_etherbone)
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# Ethernet ---------------------------------------------------------------------------------
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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self.submodules.ethphy = LiteEthPHY(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"),
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clk_freq = sys_clk_freq,
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with_hw_init_reset = False)
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self.add_csr("ethphy")
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if with_ethernet:
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self.submodules.ethphy = LiteEthPHYGMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"),
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with_hw_init_reset = False)
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platform.add_platform_command("""NET "eth_clocks_rx" CLOCK_DEDICATED_ROUTE = FALSE;""")
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self.add_csr("ethphy")
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self.add_ethernet(phy=self.ethphy)
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# Etherbone --------------------------------------------------------------------------------
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if with_etherbone:
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self.submodules.ethphy = LiteEthPHYGMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"),
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with_hw_init_reset = False)
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platform.add_platform_command("""NET "eth_clocks_rx" CLOCK_DEDICATED_ROUTE = FALSE;""")
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self.add_csr("ethphy")
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self.add_etherbone(phy=self.ethphy)
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# Leds -------------------------------------------------------------------------------------
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