Merge pull request #553 from machdyne/master
add support for mozart ml1
This commit is contained in:
enjoy-digital
GitHub
commit
2e77a18d71
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@ -174,6 +174,7 @@ Some of the suported boards, see yours? Give LiteX-Boards a try!
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├── machdyne_konfekt
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├── machdyne_kopflos
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├── machdyne_krote
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├── machdyne_mozart_ml1
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├── machdyne_noir
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├── machdyne_schoko
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├── marblemini
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@ -0,0 +1,140 @@
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#
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# This file is part of LiteX-Boards.
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#
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# Copright (c) 2023 Lone Dynamics Corporation <info@lonedynamics.com>
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#
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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from litex.build.openfpgaloader import OpenFPGALoader
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# IOs ----------------------------------------------------------------------------------------------
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_io_vx = [
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# Clock
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("clk48", 0, Pins("A7"), IOStandard("LVCMOS33")),
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# SDRAM
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("sdram_clock", 0, Pins("F16"), IOStandard("LVTTL33")),
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("sdram", 0,
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Subsignal("a", Pins(
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"M13 M14 L14 L13 G12 G13 G14 G15",
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"F12 F13 T15 F14 E14")),
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Subsignal("ba", Pins("P14 N13")),
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Subsignal("cs_n", Pins("J16")),
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Subsignal("cke", Pins("F15")),
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Subsignal("ras_n", Pins("K15")),
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Subsignal("cas_n", Pins("K16")),
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Subsignal("we_n", Pins("L15")),
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Subsignal("dq", Pins(
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"R15 R16 P16 P15 N16 N14 M16 M15",
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"E15 D16 D14 C16 C15 C14 B15 B16")),
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Subsignal("dm", Pins("L16 E16")),
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IOStandard("LVTTL33")
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),
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# Differential Data Multiple Interface
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("ddmi", 0,
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Subsignal("clk_p", Pins("B13"),
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IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
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Subsignal("data0_p", Pins("A11"),
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IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
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Subsignal("data1_p", Pins("B12"),
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IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
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Subsignal("data2_p", Pins("B10"),
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IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
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),
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# USB-C
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("usb", 0,
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Subsignal("d_p", Pins("A13")),
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Subsignal("d_n", Pins("A14")),
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Subsignal("pullup", Pins("D13")),
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IOStandard("LVCMOS33")
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),
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# DUAL USB HOST
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("usb_host", 0,
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Subsignal("dp", Pins("A9 C8")),
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Subsignal("dm", Pins("A10 B8")),
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IOStandard("LVCMOS33")
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),
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# ETHERNET
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("eth_clocks", 0,
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Subsignal("ref_clk", Pins("C7")),
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IOStandard("LVCMOS33")
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),
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("eth", 0,
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Subsignal("rx_data", Pins("E4 D4"), Misc("PULLMODE=UP")),
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Subsignal("tx_data", Pins("E6 D6")),
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Subsignal("tx_en", Pins("C5")),
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Subsignal("crs_dv", Pins("A5"), Misc("PULLMODE=UP")),
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Subsignal("rst_n", Pins("B5")),
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IOStandard("LVCMOS33")
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),
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# DEBUG UART
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("serial", 0,
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Subsignal("tx", Pins("B3")),
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Subsignal("rx", Pins("A2")),
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IOStandard("LVCMOS33")
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),
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]
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_io_v0 = [
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# SD card w/ SD-mode interface
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("sdcard", 0,
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Subsignal("cd", Pins("A6"), Misc("PULLMODE=UP")),
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Subsignal("clk", Pins("L3")),
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Subsignal("cmd", Pins("M1"), Misc("DRIVE=8 PULLMODE=UP")),
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Subsignal("data", Pins("L1 M2 M3 L2"), Misc("DRIVE=8 PULLMODE=UP")),
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Misc("SLEWRATE=FAST"),
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IOStandard("LVCMOS33")
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),
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# SD card w/ SPI interface
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("spisdcard", 0,
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Subsignal("clk", Pins("L3")),
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Subsignal("mosi", Pins("M1")),
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Subsignal("cs_n", Pins("L2")),
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Subsignal("miso", Pins("L1")),
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Misc("SLEWRATE=FAST"),
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IOStandard("LVCMOS33"),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors_vx = [
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticePlatform):
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default_clk_name = "clk48"
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default_clk_period = 1e9/48e6
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def __init__(self, revision="v0", device="45F", toolchain="trellis", **kwargs):
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assert revision in ["v0"]
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assert device in ["12F", "25F", "45F", "85F"]
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self.revision = revision
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io = _io_vx
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connectors = _connectors_vx
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if revision == "v0": io += _io_v0
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LatticePlatform.__init__(self, f"LFE5U-{device}-6BG256", io, connectors, toolchain=toolchain, **kwargs)
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def create_programmer(self, cable):
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return OpenFPGALoader(cable=cable)
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def do_finalize(self, fragment):
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LatticePlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk48", loose=True), 1e9/48e6)
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@ -0,0 +1,222 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) Lone Dynamics Corporation <info@lonedynamics.com>
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#
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# SPDX-License-Identifier: BSD-2-Clause
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#
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import os
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import sys
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import json
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from migen import *
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from litex.gen import *
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from litex_boards.platforms import machdyne_mozart_ml1
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from litex.build.io import DDROutput
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from litex.build.lattice.trellis import trellis_args, trellis_argdict
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.soc.cores.clock import *
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from litex.soc.cores.usb_ohci import USBOHCI
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from litex.soc.cores.video import VideoHDMIPHY
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.interconnect.csr_eventmanager import *
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from litedram.modules import W9825G6KH6
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from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
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from litex.soc.integration.soc import SoCRegion
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# CRG ---------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, sdram_rate):
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self.rst = Signal()
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self.cd_por = ClockDomain()
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self.cd_sys = ClockDomain()
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self.cd_init = ClockDomain()
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self.cd_video = ClockDomain()
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self.cd_video5x = ClockDomain()
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self.stop = Signal()
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self.reset = Signal()
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# Clk / Rst
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clk48 = platform.request("clk48")
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# Power on reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(clk48)
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# PLL
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self.pll = pll = ECP5PLL()
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self.comb += pll.reset.eq(~por_done | self.rst)
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pll.register_clkin(clk48, 48e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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if sdram_rate == "1:2":
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self.cd_sys2x = ClockDomain()
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self.cd_sys2x_ps = ClockDomain()
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180)
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elif sdram_rate == "1:4":
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self.cd_sys2x = ClockDomain()
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self.cd_sys4x = ClockDomain()
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self.cd_sys4x_ps = ClockDomain()
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_ps, 4*sys_clk_freq, phase=180)
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else:
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self.cd_sys_ps = ClockDomain()
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
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if sdram_rate == "1:2":
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sdram_clk = ClockSignal("sys2x_ps")
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elif sdram_rate == "1:4":
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sdram_clk = ClockSignal("sys4x_ps")
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else:
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sdram_clk = ClockSignal("sys_ps")
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self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
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pll2 = ECP5PLL()
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self.pll2 = pll2
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pll2.register_clkin(clk48, 48e6)
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pll2.create_clkout(self.cd_video, 25e6)
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pll2.create_clkout(self.cd_video5x, 125e6)
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pll3 = ECP5PLL()
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self.pll3 = pll3
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pll3.register_clkin(clk48, 48e6)
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self.cd_usb_12 = ClockDomain()
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self.cd_usb = ClockDomain()
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self.cd_usb_48 = ClockDomain()
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self.cd_usb_48 = self.cd_usb
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pll3.create_clkout(self.cd_usb, 48e6)
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pll3.create_clkout(self.cd_usb_12, 12e6)
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self.comb += pll3.reset.eq(~por_done)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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mem_map = {**SoCCore.mem_map, **{
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"usb_ohci": 0xc0000000,
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}}
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def __init__(self, revision="v0", device="45F", sdram_rate="1:2", sys_clk_freq=int(48e6), toolchain="trellis", with_usb_host=False, with_ethernet=False, **kwargs):
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platform = machdyne_mozart_ml1.Platform(revision=revision, device=device ,toolchain=toolchain)
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Mozart ML1", **kwargs)
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# DRAM -------------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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if sdram_rate == "1:2":
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sdrphy_cls = HalfRateGENSDRPHY
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elif sdram_rate == "1:4":
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sdrphy_cls = QuarterRateGENSDRPHY
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else:
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sdrphy_cls = GENSDRPHY
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self.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = W9825G6KH6(sys_clk_freq, sdram_rate),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# DDMI Framebuffer -------------------------------------------------------------------------------------
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self.videophy = VideoHDMIPHY(platform.request("ddmi"),
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clock_domain="video")
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self.add_video_framebuffer(phy=self.videophy, timings="640x480@60Hz",
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clock_domain="video", format="rgb565")
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# USB Host ---------------------------------------------------------------------------------
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if with_usb_host:
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self.usb_ohci = USBOHCI(platform, platform.request("usb_host"), usb_clk_freq=int(48e6))
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self.bus.add_slave("usb_ohci_ctrl", self.usb_ohci.wb_ctrl, region=SoCRegion(origin=self.mem_map["usb_ohci"], size=0x100000, cached=False))
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self.dma_bus.add_master("usb_ohci_dma", master=self.usb_ohci.wb_dma)
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self.comb += self.cpu.interrupt[16].eq(self.usb_ohci.interrupt)
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# Ethernet ---------------------------------------------------------------------------------
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if with_ethernet:
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from liteeth.phy.rmii import LiteEthPHYRMII
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self.ethphy = LiteEthPHYRMII(
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clock_pads = platform.request("eth_clocks"),
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pads = platform.request("eth"),
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with_hw_init_reset=True,
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refclk_cd=None)
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self.add_ethernet(phy=self.ethphy)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on Mozart ML1")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build design.")
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target_group.add_argument("--load", action="store_true", help="Load bitstream to SRAM.")
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target_group.add_argument("--flash", action="store_true", help="Flash bitstream to MMOD.")
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target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
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target_group.add_argument("--sys-clk-freq", default=48e6, help="System clock frequency.")
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target_group.add_argument("--revision", default="v0", help="Board Revision (v0).")
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target_group.add_argument("--device", default="45F", help="ECP5 device (12F, 25F, 45F or 85F).")
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target_group.add_argument("--cable", default="usb-blaster", help="Specify an openFPGALoader cable.")
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target_group.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
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target_group.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
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target_group.add_argument("--with-usb-host", action="store_true", help="Enable USB host support.")
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target_group.add_argument("--with-ethernet", action="store_true", help="Enable ethernet support.")
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target_group.add_argument("--boot-from-flash", action="store_true", help="Boot from flash MMOD.")
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builder_args(parser)
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soc_core_args(parser)
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trellis_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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toolchain = args.toolchain,
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revision = args.revision,
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device = args.device,
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_usb_host = args.with_usb_host,
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with_ethernet = args.with_ethernet,
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**soc_core_argdict(args))
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if args.with_sdcard:
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soc.add_sdcard()
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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builder = Builder(soc, **builder_argdict(args))
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builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
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if args.build:
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builder.build(**builder_kargs)
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if args.load:
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prog = soc.platform.create_programmer(args.cable)
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if args.flash:
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prog = soc.platform.create_programmer(args.cable)
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prog.flash(0x100000, builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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