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stlv7325: make VCCIO configurable

This commit is contained in:
Hans Baier 2023-04-07 09:27:03 +07:00
parent 566a753dd3
commit 2f13decc49
2 changed files with 261 additions and 255 deletions
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49
litex_boards/platforms/sitlinv_stlv7325.py
View File

@ -13,11 +13,14 @@ from litex.build.openocd import OpenOCD
# IOs ---------------------------------------------------------------------------------------------- # IOs ----------------------------------------------------------------------------------------------
def _get_io(voltage="2.5V"):
assert voltage in ["2.5V", "3.3V"]
VCCIO = str(25 if voltage == "2.5V" else 33)
_io = [ _io = [
# Clk / Rst # Clk / Rst
("cpu_reset_n", 0, Pins("AC16"), IOStandard("LVCMOS15")), ("cpu_reset_n", 0, Pins("AC16"), IOStandard("LVCMOS15")),
("clk100", 0, Pins("F17"), IOStandard("LVCMOS25")), ("clk100", 0, Pins("F17"), IOStandard("LVCMOS" + VCCIO)),
("clk200", 0, ("clk200", 0,
Subsignal("p", Pins("AB11"), IOStandard("DIFF_SSTL15")), Subsignal("p", Pins("AB11"), IOStandard("DIFF_SSTL15")),
Subsignal("n", Pins("AC11"), IOStandard("DIFF_SSTL15")) Subsignal("n", Pins("AC11"), IOStandard("DIFF_SSTL15"))
@ -49,14 +52,14 @@ _io = [
("i2c", 0, ("i2c", 0,
Subsignal("scl", Pins("U19")), Subsignal("scl", Pins("U19")),
Subsignal("sda", Pins("U20")), Subsignal("sda", Pins("U20")),
IOStandard("LVCMOS25") IOStandard("LVCMOS" + VCCIO)
), ),
# Serial # Serial
("serial", 0, ("serial", 0,
Subsignal("tx", Pins("M25")), # CH340_TX Subsignal("tx", Pins("M25")), # CH340_TX
Subsignal("rx", Pins("L25")), # CH340_RX Subsignal("rx", Pins("L25")), # CH340_RX
IOStandard("LVCMOS25") IOStandard("LVCMOS" + VCCIO)
), ),
# DDR3 SDRAM # DDR3 SDRAM
@ -119,14 +122,12 @@ _io = [
Subsignal("rx_n", Pins("R3")), Subsignal("rx_n", Pins("R3")),
Subsignal("tx_p", Pins("P2")), Subsignal("tx_p", Pins("P2")),
Subsignal("tx_n", Pins("P1")), Subsignal("tx_n", Pins("P1")),
IOStandard("LVCMOS33"),
), ),
("sata", 1, ("sata", 1,
Subsignal("rx_p", Pins("N4")), Subsignal("rx_p", Pins("N4")),
Subsignal("rx_n", Pins("N3")), Subsignal("rx_n", Pins("N3")),
Subsignal("tx_p", Pins("M2")), Subsignal("tx_p", Pins("M2")),
Subsignal("tx_n", Pins("M1")), Subsignal("tx_n", Pins("M1")),
IOStandard("LVCMOS33"),
), ),
# SDCard # SDCard
@ -136,14 +137,14 @@ _io = [
Subsignal("mosi", Pins("U21"), Misc("PULLUP True")), Subsignal("mosi", Pins("U21"), Misc("PULLUP True")),
Subsignal("miso", Pins("N16"), Misc("PULLUP True")), Subsignal("miso", Pins("N16"), Misc("PULLUP True")),
Misc("SLEW=FAST"), Misc("SLEW=FAST"),
IOStandard("LVCMOS25") IOStandard("LVCMOS" + VCCIO)
), ),
("sdcard", 0, ("sdcard", 0,
Subsignal("clk", Pins("N21")), Subsignal("clk", Pins("N21")),
Subsignal("cmd", Pins("U21"), Misc("PULLUP True")), Subsignal("cmd", Pins("U21"), Misc("PULLUP True")),
Subsignal("data", Pins("N16 U16 N22 P19"), Misc("PULLUP True")), Subsignal("data", Pins("N16 U16 N22 P19"), Misc("PULLUP True")),
Misc("SLEW=FAST"), Misc("SLEW=FAST"),
IOStandard("LVCMOS25") IOStandard("LVCMOS" + VCCIO)
), ),
# GMII Ethernet # GMII Ethernet
@ -186,18 +187,18 @@ _io = [
# HDMI out # HDMI out
("hdmi_out", 0, ("hdmi_out", 0,
Subsignal("clk_p", Pins("R21"), IOStandard("TMDS_33")), Subsignal("clk_p", Pins("R21"), IOStandard("TMDS_" + VCCIO)),
Subsignal("clk_n", Pins("P21"), IOStandard("TMDS_33")), Subsignal("clk_n", Pins("P21"), IOStandard("TMDS_" + VCCIO)),
Subsignal("data0_p", Pins("N18"), IOStandard("TMDS_33")), Subsignal("data0_p", Pins("N18"), IOStandard("TMDS_" + VCCIO)),
Subsignal("data0_n", Pins("M19"), IOStandard("TMDS_33")), Subsignal("data0_n", Pins("M19"), IOStandard("TMDS_" + VCCIO)),
Subsignal("data1_p", Pins("M21"), IOStandard("TMDS_33")), Subsignal("data1_p", Pins("M21"), IOStandard("TMDS_" + VCCIO)),
Subsignal("data1_n", Pins("M22"), IOStandard("TMDS_33")), Subsignal("data1_n", Pins("M22"), IOStandard("TMDS_" + VCCIO)),
Subsignal("data2_p", Pins("K25"), IOStandard("TMDS_33")), Subsignal("data2_p", Pins("K25"), IOStandard("TMDS_" + VCCIO)),
Subsignal("data2_n", Pins("K26"), IOStandard("TMDS_33")), Subsignal("data2_n", Pins("K26"), IOStandard("TMDS_" + VCCIO)),
Subsignal("scl", Pins("K21"), IOStandard("LVCMOS33")), Subsignal("scl", Pins("K21"), IOStandard("LVCMOS" + VCCIO)),
Subsignal("sda", Pins("L23"), IOStandard("LVCMOS33")), Subsignal("sda", Pins("L23"), IOStandard("LVCMOS" + VCCIO)),
Subsignal("hdp", Pins("N26"), IOStandard("LVCMOS33")), Subsignal("hdp", Pins("N26"), IOStandard("LVCMOS" + VCCIO)),
Subsignal("cec", Pins("M26"), IOStandard("LVCMOS33")), Subsignal("cec", Pins("M26"), IOStandard("LVCMOS" + VCCIO)),
), ),
# PCIe # PCIe
@ -272,8 +273,8 @@ _io = [
# SI5338 (optional part per seller?) # SI5338 (optional part per seller?)
("si5338_i2c", 0, ("si5338_i2c", 0,
Subsignal("sck", Pins("U19"), IOStandard("LVCMOS25")), Subsignal("sck", Pins("U19"), IOStandard("LVCMOS" + VCCIO)),
Subsignal("sda", Pins("U20"), IOStandard("LVCMOS25")) Subsignal("sda", Pins("U20"), IOStandard("LVCMOS" + VCCIO))
), ),
("si5338_clkin", 0, # CLK2A/B ("si5338_clkin", 0, # CLK2A/B
Subsignal("p", Pins("K6"), IOStandard("LVDS_25")), Subsignal("p", Pins("K6"), IOStandard("LVDS_25")),
@ -281,6 +282,8 @@ _io = [
), ),
] ]
return _io
# Connectors --------------------------------------------------------------------------------------- # Connectors ---------------------------------------------------------------------------------------
_connectors = [ _connectors = [
@ -463,8 +466,8 @@ class Platform(Xilinx7SeriesPlatform):
default_clk_name = "clk200" default_clk_name = "clk200"
default_clk_period = 1e9/200e6 default_clk_period = 1e9/200e6
def __init__(self): def __init__(self, vccio="2.5V"):
Xilinx7SeriesPlatform.__init__(self, "xc7k325t-ffg676-2", _io, _connectors, toolchain="vivado") Xilinx7SeriesPlatform.__init__(self, "xc7k325t-ffg676-2", _get_io(vccio), _connectors, toolchain="vivado")
self.add_platform_command(""" self.add_platform_command("""
set_property CFGBVS VCCO [current_design] set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 2.5 [current_design] set_property CONFIG_VOLTAGE 2.5 [current_design]

5
litex_boards/targets/sitlinv_stlv7325.py
View File

@ -71,6 +71,7 @@ class _CRG(LiteXModule):
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=100e6, def __init__(self, sys_clk_freq=100e6,
vccio = "2.5V",
with_ethernet = False, with_ethernet = False,
with_etherbone = False, with_etherbone = False,
local_ip = "192.168.1.50", local_ip = "192.168.1.50",
@ -84,7 +85,7 @@ class BaseSoC(SoCCore):
with_video_framebuffer = False, with_video_framebuffer = False,
with_video_terminal = False, with_video_terminal = False,
**kwargs): **kwargs):
platform = sitlinv_stlv7325.Platform() platform = sitlinv_stlv7325.Platform(vccio)
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
self.crg = _CRG(platform, sys_clk_freq) self.crg = _CRG(platform, sys_clk_freq)
@ -189,6 +190,7 @@ def main():
from litex.build.parser import LiteXArgumentParser from litex.build.parser import LiteXArgumentParser
parser = LiteXArgumentParser(platform=sitlinv_stlv7325.Platform, description="LiteX SoC on AliExpress STLV7325.") parser = LiteXArgumentParser(platform=sitlinv_stlv7325.Platform, description="LiteX SoC on AliExpress STLV7325.")
parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.") parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
parser.add_target_argument("--vccio", default="2.5V", type=str, help="IO Voltage (set by J4), can be 2.5V or 3.3V")
ethopts = parser.target_group.add_mutually_exclusive_group() ethopts = parser.target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.") ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.") ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
@ -212,6 +214,7 @@ def main():
soc = BaseSoC( soc = BaseSoC(
sys_clk_freq = args.sys_clk_freq, sys_clk_freq = args.sys_clk_freq,
vccio = args.vccio,
with_ethernet = args.with_ethernet, with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone, with_etherbone = args.with_etherbone,
local_ip = args.local_ip, local_ip = args.local_ip,