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sipeed_tang_mega_138k_pro: added SDRAM sipeed variant, allows user to select between mister and sipeed SDRAM module, fix sipeed SDRAM memory module

This commit is contained in:
Gwenhael Goavec-Merou 2024-08-04 11:12:15 +02:00
parent 81209b9fd1
commit 2fa838b79d
2 changed files with 71 additions and 19 deletions
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68
litex_boards/platforms/sipeed_tang_mega_138k_pro.py
View File

@ -243,23 +243,6 @@ _dock_io = [
Misc("PULL_MODE=NONE DRIVE=8")
),
("sdram_clock", 0, Pins("V23"), IOStandard("LVCMOS33")),
("sdram", 0,
Subsignal("a", Pins(
"V19 W19 U22 V22 Y25 AA25 AA24 AB25",
"AB26 AC26 Y20 U25 U24")),
Subsignal("dq", Pins(
"U16 V16 U15 V17 W21 Y21 P21 U17",
"P25 W23 T25 R25 R23 T23 P24 P23")),
Subsignal("ba", Pins("V26 W20")),
Subsignal("cas_n", Pins("W26")),
Subsignal("cs_n", Pins("U26")),
Subsignal("ras_n", Pins("W25")),
Subsignal("we_n", Pins("Y26")),
IOStandard("LVCMOS33"),
Misc("PULL_MODE=UP")
),
# RGMII Ethernet
("eth_clocks", 0,
Subsignal("tx", Pins("H24")),
@ -294,6 +277,57 @@ _dock_connectors = [
],
]
# SDRAMs -------------------------------------------------------------------------------------------
def misterSDRAM(conn="sdram_connector"):
return [
("sdram_clock", 0, Pins(f"{conn}:20"),
IOStandard("LVCMOS33"),
Misc("PULL_MODE=NONE DRIVE=16"),
),
("sdram", 0,
Subsignal("a", Pins(
f"{conn}:37 {conn}:38 {conn}:39 {conn}:40 {conn}:28 {conn}:25 {conn}:26 {conn}:23",
f"{conn}:24 {conn}:21 {conn}:36 {conn}:22 {conn}:19"),
),
Subsignal("dq", Pins(
f"{conn}:1 {conn}:2 {conn}:3 {conn}:4 {conn}:5 {conn}:6 {conn}:7 {conn}:8",
f"{conn}:18 {conn}:17 {conn}:16 {conn}:15 {conn}:14 {conn}:13 {conn}:10 {conn}:9"),
),
Subsignal("ba", Pins(f"{conn}:34 {conn}:35")),
Subsignal("cas_n", Pins(f"{conn}:31")),
Subsignal("cs_n", Pins(f"{conn}:33")),
Subsignal("ras_n", Pins(f"{conn}:32")),
Subsignal("we_n", Pins(f"{conn}:27")),
IOStandard("LVCMOS33"),
),
]
def sipeedSDRAM(conn="sdram_connector"):
return [
("sdram_clock", 0, Pins(f"{conn}:20"),
IOStandard("LVCMOS33"),
Misc("PULL_MODE=NONE DRIVE=16"),
),
("sdram", 0,
Subsignal("a", Pins(
f"{conn}:37 {conn}:38 {conn}:39 {conn}:40 {conn}:28 {conn}:25 {conn}:26 {conn}:23",
f"{conn}:24 {conn}:21 {conn}:36 {conn}:22 {conn}:19")
),
Subsignal("dq", Pins(
f"{conn}:1 {conn}:2 {conn}:3 {conn}:4 {conn}:5 {conn}:6 {conn}:7 {conn}:8",
f"{conn}:18 {conn}:17 {conn}:16 {conn}:15 {conn}:14 {conn}:13 {conn}:10 {conn}:9"),
),
Subsignal("ba", Pins(f"{conn}:34 {conn}:35")),
Subsignal("cas_n", Pins(f"{conn}:31")),
Subsignal("cs_n", Pins(f"{conn}:33")),
Subsignal("ras_n", Pins(f"{conn}:32")),
Subsignal("we_n", Pins(f"{conn}:27")),
Subsignal("dm", Pins(f"{conn}:29 {conn}:30")),
IOStandard("LVCMOS33"),
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(GowinPlatform):

22
litex_boards/targets/sipeed_tang_mega_138k_pro.py
View File

@ -22,7 +22,7 @@ from litex.soc.cores.video import *
from liteeth.phy.gw5rgmii import LiteEthPHYRGMII
from litedram.modules import AS4C32M16, MT41J256M16
from litedram.modules import AS4C32M16, MT41J256M16, W9825G6KH6
from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
from litedram.phy import GW5DDRPHY
from litex.build.io import DDROutput
@ -122,6 +122,7 @@ class BaseSoC(SoCCore):
with_video_terminal = False,
with_ddr3 = False,
with_sdram = False,
sdram_model = "sipeed",
sdram_rate = "1:2",
with_led_chaser = True,
with_rgb_led = False,
@ -129,6 +130,14 @@ class BaseSoC(SoCCore):
**kwargs):
platform = sipeed_tang_mega_138k_pro.Platform(toolchain="gowin")
assert not with_sdram or (sdram_model in ["sipeed", "mister"])
if with_sdram:
platform.add_extension({
"sipeed": sipeed_tang_mega_138k_pro.sipeedSDRAM(),
"mister": sipeed_tang_mega_138k_pro.misterSDRAM}[sdram_model]
)
# CRG --------------------------------------------------------------------------------------
cpu_clk_freq = int(800e6) if kwargs["cpu_type"] == "gowin_ae350" else 0
self.crg = _CRG(platform, sys_clk_freq, cpu_clk_freq,
@ -207,6 +216,9 @@ class BaseSoC(SoCCore):
# SDR SDRAM --------------------------------------------------------------------------------
if with_sdram and not self.integrated_main_ram_size:
module_cls = {
"sipeed": W9825G6KH6,
"mister": AS4C32M16}[sdram_model]
if sdram_rate == "1:2":
sdrphy_cls = HalfRateGENSDRPHY
else:
@ -214,7 +226,7 @@ class BaseSoC(SoCCore):
self.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram",
phy = self.sdrphy,
module = AS4C32M16(sys_clk_freq, sdram_rate),
module = module_cls(sys_clk_freq, sdram_rate),
l2_cache_size = kwargs.get("l2_size", 8192)
)
@ -226,6 +238,11 @@ def main():
parser.add_target_argument("--flash", action="store_true", help="Flash Bitstream.")
parser.add_target_argument("--sys-clk-freq", default=50e6, type=float, help="System clock frequency.")
parser.add_target_argument("--with-sdram", action="store_true", help="Enable optional SDRAM module.")
parser.add_target_argument("--sdram-model", default="sipeed", help="SDRAM module model.",
choices=[
"sipeed",
"mister"
])
parser.add_target_argument("--with-ddr3", action="store_true", help="Enable optional DDR3 module.")
parser.add_target_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
ethopts = parser.target_group.add_mutually_exclusive_group()
@ -243,6 +260,7 @@ def main():
with_video_terminal = args.with_video_terminal,
with_ddr3 = args.with_ddr3,
with_sdram = args.with_sdram,
sdram_model = args.sdram_model,
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
local_ip = args.local_ip,