targets: Update to VideoHDMIPHY.

This commit is contained in:
Florent Kermarrec 2021-09-20 09:30:32 +02:00
parent 7161ad18ec
commit 30756ce05e
4 changed files with 8 additions and 8 deletions

View file

@ -21,7 +21,7 @@ from litex.build.lattice.trellis import trellis_args, trellis_argdict
from litex.soc.cores.clock import * from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import * from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import * from litex.soc.integration.builder import *
from litex.soc.cores.video import VideoECP5HDMIPHY from litex.soc.cores.video import VideoHDMIPHY
from litex.soc.cores.led import LedChaser from litex.soc.cores.led import LedChaser
from litex.soc.interconnect.csr import * from litex.soc.interconnect.csr import *
@ -164,7 +164,7 @@ class BaseSoC(SoCCore):
# Video ------------------------------------------------------------------------------------ # Video ------------------------------------------------------------------------------------
if with_video_terminal or with_video_framebuffer: if with_video_terminal or with_video_framebuffer:
self.submodules.videophy = VideoECP5HDMIPHY(platform.request("gpdi"), clock_domain="hdmi") self.submodules.videophy = VideoHDMIPHY(platform.request("gpdi"), clock_domain="hdmi")
if with_video_terminal: if with_video_terminal:
self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi") self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
if with_video_framebuffer: if with_video_framebuffer:

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@ -19,7 +19,7 @@ from litex.build.lattice.trellis import trellis_args, trellis_argdict
from litex.soc.cores.clock import * from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import * from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import * from litex.soc.integration.builder import *
from litex.soc.cores.video import VideoECP5HDMIPHY from litex.soc.cores.video import VideoHDMIPHY
from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
@ -92,7 +92,7 @@ class BaseSoC(SoCCore):
# Video ------------------------------------------------------------------------------------ # Video ------------------------------------------------------------------------------------
if with_video_terminal: if with_video_terminal:
self.submodules.videophy = VideoECP5HDMIPHY(platform.request("hdmi"), clock_domain="hdmi", pn_swap=["g", "b"]) self.submodules.videophy = VideoHDMIPHY(platform.request("hdmi"), clock_domain="hdmi", pn_swap=["g", "b"])
self.add_video_terminal(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi") self.add_video_terminal(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi")
# Build -------------------------------------------------------------------------------------------- # Build --------------------------------------------------------------------------------------------

View file

@ -21,7 +21,7 @@ from litex.build.lattice.trellis import trellis_args, trellis_argdict
from litex.soc.cores.clock import * from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import * from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import * from litex.soc.integration.builder import *
from litex.soc.cores.video import VideoECP5HDMIPHY from litex.soc.cores.video import VideoHDMIPHY
from litex.soc.cores.led import LedChaser from litex.soc.cores.led import LedChaser
from litex.soc.interconnect.csr import * from litex.soc.interconnect.csr import *
@ -124,7 +124,7 @@ class BaseSoC(SoCCore):
# Video ------------------------------------------------------------------------------------ # Video ------------------------------------------------------------------------------------
if with_video_terminal or with_video_framebuffer: if with_video_terminal or with_video_framebuffer:
self.submodules.videophy = VideoECP5HDMIPHY(platform.request("gpdi"), clock_domain="hdmi") self.submodules.videophy = VideoHDMIPHY(platform.request("gpdi"), clock_domain="hdmi")
if with_video_terminal: if with_video_terminal:
self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi") self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
if with_video_framebuffer: if with_video_framebuffer:

View file

@ -23,7 +23,7 @@ from litex.build.lattice.trellis import trellis_args, trellis_argdict
from litex.soc.cores.clock import * from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import * from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import * from litex.soc.integration.builder import *
from litex.soc.cores.video import VideoECP5HDMIPHY from litex.soc.cores.video import VideoHDMIPHY
from litex.soc.cores.led import LedChaser from litex.soc.cores.led import LedChaser
from litex.soc.cores.spi import SPIMaster from litex.soc.cores.spi import SPIMaster
from litex.soc.cores.gpio import GPIOOut from litex.soc.cores.gpio import GPIOOut
@ -121,7 +121,7 @@ class BaseSoC(SoCCore):
# Video ------------------------------------------------------------------------------------ # Video ------------------------------------------------------------------------------------
if with_video_terminal or with_video_framebuffer: if with_video_terminal or with_video_framebuffer:
self.submodules.videophy = VideoECP5HDMIPHY(platform.request("gpdi"), clock_domain="hdmi") self.submodules.videophy = VideoHDMIPHY(platform.request("gpdi"), clock_domain="hdmi")
if with_video_terminal: if with_video_terminal:
self.add_video_terminal(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi") self.add_video_terminal(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi")
if with_video_framebuffer: if with_video_framebuffer: