Merge pull request #348 from hubmartin/ecp5-vip
Draft: Add Lattice ECP5 VIP board + HDMI output board support
This commit is contained in:
enjoy-digital
GitHub
commit
30afe26669
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2019 Arnaud Durand <arnaud.durand@unifr.ch>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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from litex.build.lattice.programmer import OpenOCDJTAGProgrammer
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import os
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk27", 0, Pins("E17"), IOStandard("LVCMOS33")), ##
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("clk100", 0, Pins("C5"), IOStandard("LVDS")), ##
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("ext_clk50", 0, Pins("B11"), IOStandard("LVCMOS33")),
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("ext_clk50_en", 0, Pins("C11"), IOStandard("LVCMOS33")),
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("rst_n", 0, Pins("AH1"), IOStandard("LVCMOS33")),##
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# Leds
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("user_led", 0, Pins("AG30"), IOStandard("LVCMOS25")),
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("user_led", 1, Pins("AK29"), IOStandard("LVCMOS25")),
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("user_led", 2, Pins("AK30"), IOStandard("LVCMOS25")),
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("user_led", 3, Pins("AH32"), IOStandard("LVCMOS25")),
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("user_led", 4, Pins("AG32"), IOStandard("LVCMOS25")),
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("user_led", 5, Pins("AJ29"), IOStandard("LVCMOS25")),
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("user_led", 6, Pins("AM28"), IOStandard("LVCMOS25")),
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("user_led", 7, Pins("AM29"), IOStandard("LVCMOS25")),
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# ws2812
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("ws2812", 0, Pins("AK31"), IOStandard("LVCMOS25")),
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# Buttons
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("user_dip_btn", 1, Pins("J1"), IOStandard("LVCMOS33")),
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("user_dip_btn", 2, Pins("H1"), IOStandard("LVCMOS33")),
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("user_dip_btn", 3, Pins("K1"), IOStandard("LVCMOS33")),
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("user_dip_btn", 4, Pins("E15"), IOStandard("LVCMOS25")),
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("user_dip_btn", 5, Pins("D16"), IOStandard("LVCMOS25")),
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("user_dip_btn", 6, Pins("B16"), IOStandard("LVCMOS25")),
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("user_dip_btn", 7, Pins("C16"), IOStandard("LVCMOS25")),
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("user_dip_btn", 8, Pins("A16"), IOStandard("LVCMOS25")),
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("button_1", 0, Pins("P4"), IOStandard("LVCMOS25")),
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# Serial
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("serial", 0,
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Subsignal("rx", Pins("AL28"), IOStandard("LVCMOS25")), ##LVCMOS25
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Subsignal("tx", Pins("AK28"), IOStandard("LVCMOS25")), ##LVCMOS25
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),
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# DDR3 SDRAM
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("ddram", 0,
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Subsignal("a", Pins(
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" W4 Y5 AB6 P3 AB5 W5 AC6 Y7",
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"AC7 AD6 W1 Y6 U1 AD7"),
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IOStandard("SSTL135_I")),
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Subsignal("ba", Pins("U3 Y4 W3"), IOStandard("SSTL135_I")),
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Subsignal("ras_n", Pins("C2"), IOStandard("SSTL135_I")),
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Subsignal("cas_n", Pins("T1"), IOStandard("SSTL135_I")),
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Subsignal("we_n", Pins("P1"), IOStandard("SSTL135_I")),
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Subsignal("cs_n", Pins("P2"), IOStandard("SSTL135_I")),
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Subsignal("dm", Pins("AB3 R6 F2 H6"), IOStandard("SSTL135_I")),
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Subsignal("dq", Pins(
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"AC5 AC2 AB4 AE3 W2 AD4 Y1 AB1",
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"V6 P4 V7 T7 U6 T4 U7 U4",
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"H2 K1 F1 L2 E1 K3 H3 H1",
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"N7 J6 L4 K7 P7 L7 K6 H5"),
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IOStandard("SSTL135_I"),
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Misc("TERMINATION=75")),
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Subsignal("dqs_p", Pins("AC3 R4 K2 N3"), IOStandard("SSTL135D_I"),
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Misc("TERMINATION=OFF"),
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Misc("DIFFRESISTOR=100")),
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Subsignal("clk_p", Pins("R3 J4"), IOStandard("SSTL135D_I")),
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Subsignal("cke", Pins("T2"), IOStandard("SSTL135_I")),
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Subsignal("odt", Pins("V1"), IOStandard("SSTL135_I")),
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Subsignal("reset_n", Pins("C4"), IOStandard("SSTL135_I")),
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Misc("SLEWRATE=FAST"),
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),
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# SPIFlash
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("spiflash", 0,
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Subsignal("cs_n", Pins("AJ3"), IOStandard("LVCMOS33")),
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Subsignal("mosi", Pins("AK2"), IOStandard("LVCMOS33")),
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Subsignal("miso", Pins("AJ2"), IOStandard("LVCMOS33")),
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#Subsignal("wp", Pins("Y2"), IOStandard("LVCMOS33")),
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#Subsignal("hold", Pins("W1"), IOStandard("LVCMOS33")),
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),
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("R2"), IOStandard("LVCMOS33")),
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Subsignal("dq", Pins("W2 V2 Y2 W1"), IOStandard("LVCMOS33")),
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),
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# HDMI
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("hdmi", 0,
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Subsignal("clk", Pins("E25")),
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Subsignal("hsync_n", Pins("D25")),
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Subsignal("vsync_n", Pins("A25")),
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Subsignal("de", Pins("C25")),
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Subsignal("r", Pins("AE27 AD27 AB29 AB30 AB28 AB27 AC26 Y27 D24 W28 F25 F17")),
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Subsignal("g", Pins("AD26 T26 R26 A24 T32 AC30 AB31 V32 W32 Y26 W30 T30")),
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Subsignal("b", Pins("T31 R32 Y32 W31 T29 U28 V27 V26 AC31 AB32 AC32 AD32")),
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Subsignal("sda", Pins("AJ1")),
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Subsignal("scl", Pins("AG1")),
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IOStandard("LVCMOS25")
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticePlatform):
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default_clk_name = "clk12"
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default_clk_period = 1e9/12e6
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def __init__(self, toolchain="trellis", **kwargs):
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LatticePlatform.__init__(self, "LFE5UM-85F-8BG756", _io, toolchain=toolchain, **kwargs)
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def request(self, *args, **kwargs):
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import time
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if "serial" in args:
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msg = "FT2232H will be used as serial, make sure that:\n"
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msg += " -the hardware has been modified: R22 and R23 should be removed, two 0 Ω resistors shoud be populated on R34 and R35.\n"
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msg += " -the chip is configured as UART with virtual COM on port B (With FTProg or https://github.com/trabucayre/fixFT2232_ecp5evn)."
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print(msg)
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time.sleep(2)
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if "ext_clk50" in args:
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print("An oscillator must be populated on X5.")
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time.sleep(2)
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return LatticePlatform.request(self, *args, **kwargs)
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def create_programmer(self):
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return OpenOCDJTAGProgrammer("openocd_evn_ecp5.cfg")
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def do_finalize(self, fragment):
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LatticePlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk12", loose=True), 1e9/12e6)
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self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6)
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@ -0,0 +1,224 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2019 Arnaud Durand <arnaud.durand@unifr.ch>
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# Copyright (c) 2022 Martin Hubacek @hubmartin (Twitter)
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import ecp5_vip
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT41K64M16
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from litedram.phy import ECP5DDRPHY
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from litex.soc.cores.video import VideoVGAPHY
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from litex.soc.cores.bitbang import I2CMaster
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG_VERSA(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_init = ClockDomain()
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self.clock_domains.cd_por = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys2x = ClockDomain()
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self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
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# # #
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self.stop = Signal()
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self.reset = Signal()
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# Clk / Rst
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clk100 = platform.request("clk100")
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rst_n = platform.request("rst_n")
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# Power on reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(clk100)
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# PLL
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self.submodules.pll = pll = ECP5PLL()
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self.comb += pll.reset.eq(~por_done | ~rst_n | self.rst)
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pll.register_clkin(clk100, 100e6)
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pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
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pll.create_clkout(self.cd_init, 25e6)
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self.specials += [
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Instance("ECLKSYNCB",
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i_ECLKI = self.cd_sys2x_i.clk,
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i_STOP = self.stop,
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o_ECLKO = self.cd_sys2x.clk),
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Instance("CLKDIVF",
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p_DIV = "2.0",
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i_ALIGNWD = 0,
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i_CLKI = self.cd_sys2x.clk,
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i_RST = self.reset,
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o_CDIVX = self.cd_sys.clk),
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AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
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AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset),
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]
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# HDMI
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self.clock_domains.cd_hdmi = ClockDomain(reset_less=True)
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#pll.create_clkout(self.cd_hdmi, 148.5e6) # for terminal "1920x1080@60Hz"
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#pll.create_clkout(self.cd_hdmi, 160e6) # for terminal "1920x1080@60Hz"
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#pll.create_clkout(self.cd_hdmi, 80e6) # for terminal "1920x1080@30Hz"
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pll.create_clkout(self.cd_hdmi, 40e6) # for terminal "800x600@60Hz"
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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#mem_map = {**SoCCore.mem_map, **{"spiflash": 0x1000000}}
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def __init__(self, sys_clk_freq=int(50e6), toolchain="trellis",
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with_led_chaser=True,
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with_video_terminal=True,
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with_video_framebuffer=False,**kwargs):
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platform = ecp5_vip.Platform(toolchain=toolchain)
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#bios_flash_offset = 0x400000
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# Set CPU variant / reset address
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#kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
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kwargs["integrated_rom_size"] = 0x10000
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on ECP5 Evaluation Board",
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#ident_version = True,
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#integrated_main_ram_size = 0x4000,
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integrated_main_ram_size = 0,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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crg_cls = _CRG_VERSA
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self.submodules.crg = crg_cls(platform, sys_clk_freq)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if crg_cls == _CRG_VERSA:
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self.submodules.ddrphy = ECP5DDRPHY(
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platform.request("ddram"),
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sys_clk_freq=sys_clk_freq)
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self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
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self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41K64M16(sys_clk_freq, "1:2"), # Not entirely MT41J64M16 but similar and works(c)
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l2_cache_size = kwargs.get("l2_size", 8192),
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)
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# Video ------------------------------------------------------------------------------------
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if with_video_terminal or with_video_framebuffer:
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pads = platform.request("hdmi")
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self.submodules.videophy = VideoVGAPHY(pads, clock_domain="hdmi")
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self.submodules.videoi2c = I2CMaster(pads)
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# # 1920x1080@60Hz
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# pixel_clock_hz = 160e6
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# framerate_hz = 60
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# pixels_horizontal = 2200
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# pixels_vertical = 1125
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# 800x600@60Hz
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pixel_clock_hz = 40e6
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framerate_hz = 60
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pixels_horizontal = 1056
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pixels_vertical = 628
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# # 1920x1080@30Hz
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# pixel_clock_hz = 80e6
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# framerate_hz = 30
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# pixels_horizontal = 2640
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# pixels_vertical = 1125
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self.videoi2c.add_init(addr=0x3B, init=[
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(0xc7, 0x00), # HDMI configuration
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(0xc7, 0x00), # Write twice, the first transfer fails for some reason
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(0x1e, 0x00), # Power up transmitter
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(0x08, 0x60), # Input Bus/Pixel Repetition (default)
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(0x00, int((pixel_clock_hz/1e4) %256)), # Pixel clock in MHz * 100
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(0x01, int((pixel_clock_hz/1e4)//256)), #
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(0x02, int((framerate_hz*100) %256)), # Framerate * 100
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(0x03, int((framerate_hz*100)//256)), #
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(0x04, int((pixels_horizontal) %256)), # Pixels horizontal
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(0x05, int((pixels_horizontal)//256)), #
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(0x06, int((pixels_vertical) %256)), # Pixels vertical
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(0x07, int((pixels_vertical)//256)), #
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(0x1a, 0x00) # end
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])
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if with_video_terminal:
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#self.add_video_terminal(phy=self.videophy, timings="1920x1080@60Hz", clock_domain="hdmi")
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#self.add_video_terminal(phy=self.videophy, timings="1920x1080@30Hz", clock_domain="hdmi")
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self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
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if with_video_framebuffer:
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#self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
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self.add_video_framebuffer(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Running code from SPI flash had some side effects on BIOS with enabled DDR3 memory
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# So I reverted to the FPGA BRAM for BIOS.
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# # SPI Flash --------------------------------------------------------------------------------
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# from litespi.modules import MX25L12835F
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# from litespi.opcodes import SpiNorFlashOpCodes as Codes
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# self.add_spi_flash(mode="1x", module=MX25L12835F(Codes.READ_1_1_1), with_master=False)
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# # Add ROM linker region --------------------------------------------------------------------
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# self.bus.add_region("rom", SoCRegion(
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# origin = self.mem_map["spiflash"] + bios_flash_offset,
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# size = (16-4)*1024*1024,
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# linker = True)
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# )
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on ECP5 Evaluation Board")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain: trellis (default) or diamond")
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parser.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency (default: 60MHz)")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(toolchain=args.toolchain,
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sys_clk_freq = int(float(args.sys_clk_freq)),
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**soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".svf"))
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if __name__ == "__main__":
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main()
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