efinix_xyloni_dev_kit: Update SPI Flash.
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16171282c8
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30cacc19c2
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@ -44,17 +44,15 @@ class _CRG(Module):
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
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def __init__(self, bios_flash_offset, sys_clk_freq, with_led_chaser=True, **kwargs):
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platform = efinix_xyloni_dev_kit.Platform()
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# Disable Integrated ROM since too large for this device.
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# Disable Integrated ROM.
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kwargs["integrated_rom_size"] = 0
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# Set CPU variant / reset address
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if kwargs.get("cpu_type", "vexriscv") == "vexriscv":
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kwargs["cpu_variant"] = "minimal"
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kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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@ -72,10 +70,13 @@ class BaseSoC(SoCCore):
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# Add ROM linker region --------------------------------------------------------------------
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self.bus.add_region("rom", SoCRegion(
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origin = self.mem_map["spiflash"] + bios_flash_offset,
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origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
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size = 32*kB,
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linker = True)
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)
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# Set CPU reset address to ROM.
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if hasattr(self.cpu, "set_reset_address"):
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self.cpu.set_reset_address(self.bus.regions["rom"].origin)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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