mng_rkx7: Add SPI Flash support.

litex_boards/platforms/mnt_rkx7.py

@@ -21,6 +21,13 @@ _io = [
         IOStandard("LVCMOS33")
     ),
 
+    # SPIFlash
+    ("spiflash4x", 0,  # clock needs to be accessed through STARTUPE2
+        Subsignal("cs_n", Pins("C23")),
+        Subsignal("dq",   Pins("B24 A25 B22 A22")),
+        IOStandard("LVCMOS33")
+    ),
+
     # DDR3 SDRAM.
     ("ddram", 0,
         Subsignal("a",       Pins(

litex_boards/targets/mnt_rkx7.py

@@ -44,7 +44,7 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(100e6), **kwargs):
+    def __init__(self, sys_clk_freq=int(100e6), with_spi_flash=False, **kwargs):
         platform = mnt_rkx7.Platform()
 
         # SoCCore ----------------------------------------------------------------------------------
@@ -69,6 +69,12 @@ class BaseSoC(SoCCore):
                 l2_cache_size = kwargs.get("l2_size", 8192),
             )
 
+        # SPI Flash --------------------------------------------------------------------------------
+        if with_spi_flash:
+            from litespi.modules import W25Q128JV
+            from litespi.opcodes import SpiNorFlashOpCodes as Codes
+            self.add_spi_flash(mode="4x", module=W25Q128JV(Codes.READ_1_1_4), rate="1:1", with_master=True)
+
 # Build --------------------------------------------------------------------------------------------
 
 def main():
@@ -76,12 +82,14 @@ def main():
     parser.add_argument("--build",          action="store_true", help="Build bitstream")
     parser.add_argument("--load",           action="store_true", help="Load bitstream")
     parser.add_argument("--sys-clk-freq",   default=100e6,       help="System clock frequency (default: 100MHz)")
+    parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed)")
     builder_args(parser)
     soc_core_args(parser)
     args = parser.parse_args()
 
     soc = BaseSoC(
         sys_clk_freq   = int(float(args.sys_clk_freq)),
+        with_spi_flash = args.with_spi_flash,
         **soc_core_argdict(args)
     )
     builder = Builder(soc, **builder_argdict(args))