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mng_rkx7: Add SPI Flash support.

This commit is contained in:
Florent Kermarrec 2021-09-30 11:29:56 +02:00
parent df7fe5687e
commit 31b404c42f
2 changed files with 19 additions and 4 deletions
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7
litex_boards/platforms/mnt_rkx7.py
View File

@ -21,6 +21,13 @@ _io = [
IOStandard("LVCMOS33") IOStandard("LVCMOS33")
), ),
# SPIFlash
("spiflash4x", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("C23")),
Subsignal("dq", Pins("B24 A25 B22 A22")),
IOStandard("LVCMOS33")
),
# DDR3 SDRAM. # DDR3 SDRAM.
("ddram", 0, ("ddram", 0,
Subsignal("a", Pins( Subsignal("a", Pins(

16
litex_boards/targets/mnt_rkx7.py
View File

@ -44,7 +44,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(100e6), **kwargs): def __init__(self, sys_clk_freq=int(100e6), with_spi_flash=False, **kwargs):
platform = mnt_rkx7.Platform() platform = mnt_rkx7.Platform()
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
@ -69,19 +69,27 @@ class BaseSoC(SoCCore):
l2_cache_size = kwargs.get("l2_size", 8192), l2_cache_size = kwargs.get("l2_size", 8192),
) )
# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:
from litespi.modules import W25Q128JV
from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="4x", module=W25Q128JV(Codes.READ_1_1_4), rate="1:1", with_master=True)
# Build -------------------------------------------------------------------------------------------- # Build --------------------------------------------------------------------------------------------
def main(): def main():
parser = argparse.ArgumentParser(description="LiteX SoC on MNT-RKX7") parser = argparse.ArgumentParser(description="LiteX SoC on MNT-RKX7")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)") parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)")
parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed)")
builder_args(parser) builder_args(parser)
soc_core_args(parser) soc_core_args(parser)
args = parser.parse_args() args = parser.parse_args()
soc = BaseSoC( soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)), sys_clk_freq = int(float(args.sys_clk_freq)),
with_spi_flash = args.with_spi_flash,
**soc_core_argdict(args) **soc_core_argdict(args)
) )
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))