add test/test_targets (only test platforms with simple target for now)

litex_boards/official/targets/simple.py

@@ -0,0 +1,77 @@
+#!/usr/bin/env python3
+
+# This file is Copyright (c) 2014-2019 Florent Kermarrec <florent@enjoy-digital.fr>
+# This file is Copyright (c) 2013-2014 Sebastien Bourdeauducq <sb@m-labs.hk>
+# License: BSD
+
+import argparse
+import importlib
+
+from migen import *
+from migen.genlib.io import CRG
+
+from litex.soc.integration.soc_core import *
+from litex.soc.integration.builder import *
+
+from liteeth.phy import LiteEthPHY
+from liteeth.mac import LiteEthMAC
+
+# BaseSoC ------------------------------------------------------------------------------------------
+
+class BaseSoC(SoCCore):
+    def __init__(self, platform, **kwargs):
+        sys_clk_freq = int(1e9/platform.default_clk_period)
+        SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
+            integrated_rom_size=0x8000,
+            integrated_main_ram_size=16*1024,
+            **kwargs)
+        self.submodules.crg = CRG(platform.request(platform.default_clk_name))
+
+# EthernetSoC --------------------------------------------------------------------------------------
+
+class EthernetSoC(BaseSoC):
+    mem_map = {
+        "ethmac": 0x30000000,  # (shadow @0xb0000000)
+    }
+    mem_map.update(BaseSoC.mem_map)
+
+    def __init__(self, platform, **kwargs):
+        BaseSoC.__init__(self, platform, **kwargs)
+
+        self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"),
+                                            platform.request("eth"))
+        self.add_csr("ethphy")
+        self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
+            interface="wishbone", endianness=self.cpu.endianness, with_preamble_crc=False)
+        self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
+        self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
+        self.add_csr("ethmac")
+        self.add_interrupt("ethmac")
+
+# Build --------------------------------------------------------------------------------------------
+
+def main():
+    parser = argparse.ArgumentParser(description="Generic LiteX SoC")
+    builder_args(parser)
+    soc_core_args(parser)
+    parser.add_argument("--with-ethernet", action="store_true",
+                        help="enable Ethernet support")
+    parser.add_argument("platform",
+                        help="module name of the platform to build for")
+    parser.add_argument("--gateware-toolchain", default=None,
+                        help="FPGA gateware toolchain used for build")
+    args = parser.parse_args()
+
+    platform_module = importlib.import_module(args.platform)
+    if args.gateware_toolchain is not None:
+        platform = platform_module.Platform(toolchain=args.gateware_toolchain)
+    else:
+        platform = platform_module.Platform()
+    cls = EthernetSoC if args.with_ethernet else BaseSoC
+    soc = cls(platform, **soc_core_argdict(args))
+    builder = Builder(soc, **builder_argdict(args))
+    builder.build()
+
+
+if __name__ == "__main__":
+    main()

test/test_targets.py

@@ -0,0 +1,86 @@
+# This file is Copyright (c) 2017-2019 Florent Kermarrec <florent@enjoy-digital.fr>
+# This file is Copyright (c) 2019 Tim 'mithro' Ansell <me@mith.ro>
+# License: BSD
+
+import subprocess
+import unittest
+import os
+
+from migen import *
+
+from litex.soc.integration.builder import *
+
+
+RUNNING_ON_TRAVIS = (os.getenv('TRAVIS', 'false').lower() == 'true')
+
+
+def build_test(socs):
+    errors = 0
+    for soc in socs:
+        os.system("rm -rf build")
+        builder = Builder(soc, output_dir="./build", compile_software=False, compile_gateware=False)
+        builder.build()
+        errors += not os.path.isfile("./build/gateware/top.v")
+    os.system("rm -rf build")
+    return errors
+
+
+class TestTargets(unittest.TestCase):
+    # Build simple design for all platforms
+    def test_simple(self):
+        platforms = []
+
+        # Xilinx Spartan6
+        platforms += [("official", "minispartan6")]
+        platforms += [("community", "sp605")]
+
+        # Xilinx Artix7
+        platforms += [("official", "arty")]
+        platforms += [("official", "nexys4ddr")]
+        platforms += [("official", "nexys_video")]
+        platforms += [("partner", "netv2")]
+        platforms += [("community", "ac701")]
+
+        # Xilinx Kintex7
+        platforms += [("official", "kc705")]
+        platforms += [("official", "genesys2")]
+
+        # Intel Cyclone4
+        platforms += [("official", "de0nano")]
+        platforms += [("community", "de2_115")]
+
+        # Intel Cyclone5
+        platforms += [("community", "de1soc")]
+
+        # Intel Max10
+        platforms += [("community", "de10lite")]
+
+        # Lattice iCE40
+        platforms += [("partner", "tinyfpga_bx")]
+        platforms += [("partner", "fomu_evt")]
+        platforms += [("partner", "fomu_hacker")]
+        platforms += [("partner", "fomu_pvt")]
+
+        # Lattice MachXO2
+        platforms += [("official", "machxo3")]
+
+        # Lattice ECP3
+        platforms += [("official", "versa_ecp3")]
+
+        # Lattice ECP5
+        platforms += [("official", "versa_ecp5")]
+        platforms += [("partner", "ulx3s")]
+
+        # Microsemi PolarFire
+        platforms += [("official", "avalanche")]
+
+        for s, p in platforms:
+            with self.subTest(platform=p):
+                cmd = """\
+litex_boards/official/targets/simple.py litex_boards.{s}.platforms.{p} \
+    --cpu-type=vexriscv     \
+    --no-compile-software   \
+    --no-compile-gateware   \
+    --uart-stub=True        \
+""".format(s=s, p=p)
+                subprocess.check_call(cmd, shell=True)