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antmicro_datacenter: add missing peripherals 

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
Alessandro Comodi 2022-03-15 15:22:32 +01:00
parent 77cb866233
commit 33516a40f4
2 changed files with 27 additions and 16 deletions
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28
litex_boards/platforms/antmicro_datacenter_ddr4_test_board.py
View File

@ -29,9 +29,10 @@ _io = [
Subsignal("rx", Pins("F25")),
IOStandard("LVCMOS33")
),
("serial", 1,
Subsignal("tx", Pins("D26")),
Subsignal("rx", Pins("E25")),
("spiflash4x", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("C23")),
Subsignal("dq", Pins("B24", "A25", "B22", "A22")),
IOStandard("LVCMOS33")
),
@ -98,12 +99,12 @@ _io = [
# HyperRAM
("hyperram", 0,
Subsignal("clk_n", Pins("AE26"), IOStandard("TMDS_33")),
Subsignal("clk_p", Pins("AD26"), IOStandard("TMDS_33")),
Subsignal("rst_n", Pins("AC24"), IOStandard("LVCMOS33")),
Subsignal("cs_n", Pins("AC26"), IOStandard("LVCMOS33")),
Subsignal("dq", Pins("AE23 AD25 AF24 AE22 AF23 AF25 AE25 AD24"), IOStandard("LVCMOS33")),
Subsignal("rwds", Pins("AD23"), IOStandard("LVCMOS33")),
Subsignal("clk", Pins("AD26")), # clk_n AE26
Subsignal("rst_n", Pins("AC24")),
Subsignal("cs_n", Pins("AC26")),
Subsignal("dq", Pins("AE23 AD25 AF24 AE22 AF23 AF25 AE25 AD24")),
Subsignal("rwds", Pins("AD23")),
IOStandard("LVCMOS33")
),
# SD Card
@ -118,9 +119,9 @@ _io = [
# I2C
("i2c", 0,
Subsignal("scl", Pins("Y5")),
Subsignal("sda", Pins("Y6")),
IOStandard("SSTL12_T_DCI"),
Subsignal("scl", Pins("E25")),
Subsignal("sda", Pins("D26")),
IOStandard("LVCMOS33"),
),
# HDMI Out
@ -155,7 +156,8 @@ class Platform(XilinxPlatform):
self.add_platform_command("set_property DCI_CASCADE {{32 34}} [get_iobanks 33]")
def create_programmer(self):
return OpenOCD("openocd_xc7_ft4232.cfg", "bscan_spi_xc7k100t.bit")
bscan_spi = "bscan_spi_xc7k160t.bit" if "xc7k160t" in self.device else "bscan_spi_xc7k160t.bit"
return OpenOCD("openocd_xc7_ft4232.cfg", bscan_spi)
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)

15
litex_boards/targets/antmicro_datacenter_ddr4_test_board.py
View File

@ -31,6 +31,9 @@ from litedram.common import PhySettings, GeomSettings, TimingSettings
from liteeth.phy import LiteEthS7PHYRGMII
from litex.soc.cores.hyperbus import HyperRAM
from litespi.modules import S25FL128S0
from litespi.opcodes import SpiNorFlashOpCodes as Codes
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
@ -71,8 +74,8 @@ class _CRG(Module):
class BaseSoC(SoCCore):
def __init__(self, *, sys_clk_freq=int(100e6), iodelay_clk_freq=200e6,
with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
with_hyperram=False, with_sdcard=False, with_jtagbone=True, with_uartbone=False,
with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_reset_time="10e-3", eth_dynamic_ip=False,
with_hyperram=False, with_sdcard=False, with_jtagbone=True, with_uartbone=False, with_spi_flash=False,
with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False, **kwargs):
platform = datacenter_ddr4_test_board.Platform()
@ -144,6 +147,10 @@ class BaseSoC(SoCCore):
if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:
self.add_spi_flash(mode="4x", module=S25FL128S0(Codes.READ_1_1_4), with_master=True)
# System I2C (behing multiplexer) ----------------------------------------------------------
i2c_pads = platform.request('i2c')
self.submodules.i2c = I2CMaster(i2c_pads)
@ -180,7 +187,7 @@ def main():
target_group.add_argument("--flash", action="store_true", help="Flash bitstream")
target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency")
target_group.add_argument("--iodelay-clk-freq", default=200e6, help="IODELAYCTRL frequency")
ethopts = target.add_mutually_exclusive_group()
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Add Ethernet")
ethopts.add_argument("--with-etherbone", action="store_true", help="Add EtherBone")
target_group.add_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address")
@ -192,6 +199,7 @@ def main():
target_group.add_argument("--with-uartbone", action="store_true", help="Add UartBone on 2nd serial")
target_group.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI)")
target_group.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI)")
target_group.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
@ -210,6 +218,7 @@ def main():
with_sdcard = args.with_sdcard,
with_jtagbone = args.with_jtagbone,
with_uartbone = args.with_uartbone,
with_spi_flash = args.with_spi_flash,
with_video_terminal = args.with_video_terminal,
with_video_framebuffer = args.with_video_framebuffer,
**soc_core_argdict(args))