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Merge pull request #485 from hansfbaier/master 

QMTech Artix7 boards: DDR3 RAM works on 1.5V, not 1.35V
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enjoy-digital 2023-03-28 23:16:54 +02:00 committed by GitHub
parent 3308b6ddf3 74c8569a5c
commit 33c4657cc4
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 30 additions and 30 deletions
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30
litex_boards/platforms/qmtech_artix7_fbg484.py
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@ -39,29 +39,29 @@ _io = [
# MT41K128M16JT-125K
("ddram", 0,
Subsignal("a", Pins("A15 D14 A14 D15 E14 F14 E13 C13 E16 B13 C17 F13 F16 A13"),
IOStandard("SSTL135")),
Subsignal("ba", Pins("D16 E17 B15"), IOStandard("SSTL135")),
Subsignal("ras_n", Pins("B17"), IOStandard("SSTL135")),
Subsignal("cas_n", Pins("B16"), IOStandard("SSTL135")),
Subsignal("we_n", Pins("A16"), IOStandard("SSTL135")),
IOStandard("SSTL15")),
Subsignal("ba", Pins("D16 E17 B15"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("B17"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("B16"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("A16"), IOStandard("SSTL15")),
# cs_n is hardwired on the board
#Subsignal("cs_n", Pins(""), IOStandard("SSTL135")),
Subsignal("dm", Pins("F19 D20"), IOStandard("SSTL135")),
#Subsignal("cs_n", Pins(""), IOStandard("SSTL15")),
Subsignal("dm", Pins("F19 D20"), IOStandard("SSTL15")),
Subsignal("dq", Pins(
"B20 A18 A20 D19 A19 C18 C19 E19 C20 D22 D21 E21 C22 G21 B22 E22"),
IOStandard("SSTL135"),
IOStandard("SSTL15"),
Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("dqs_p", Pins("F18 B21"),
IOStandard("DIFF_SSTL135"),
IOStandard("DIFF_SSTL15"),
Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("dqs_n", Pins("E18 A21"),
IOStandard("DIFF_SSTL135"),
IOStandard("DIFF_SSTL15"),
Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("clk_p", Pins("C14"), IOStandard("DIFF_SSTL135")),
Subsignal("clk_n", Pins("C15"), IOStandard("DIFF_SSTL135")),
Subsignal("cke", Pins("B18"), IOStandard("SSTL135")),
Subsignal("odt", Pins("D17"), IOStandard("SSTL135")),
Subsignal("reset_n", Pins("F15"), IOStandard("SSTL135")),
Subsignal("clk_p", Pins("C14"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_n", Pins("C15"), IOStandard("DIFF_SSTL15")),
Subsignal("cke", Pins("B18"), IOStandard("SSTL15")),
Subsignal("odt", Pins("D17"), IOStandard("SSTL15")),
Subsignal("reset_n", Pins("F15"), IOStandard("SSTL15")),
Misc("SLEW=FAST"),
),
]

30
litex_boards/platforms/qmtech_artix7_fgg676.py
View File

@ -39,29 +39,29 @@ _io = [
# MT41K128M16JT-125K
("ddram", 0,
Subsignal("a", Pins("E17 G17 F17 C17 G16 D16 H16 E16 H14 F15 F20 H15 C18 G15"),
IOStandard("SSTL135")),
Subsignal("ba", Pins("B17 D18 A17"), IOStandard("SSTL135")),
Subsignal("ras_n", Pins("A19"), IOStandard("SSTL135")),
Subsignal("cas_n", Pins("B19"), IOStandard("SSTL135")),
Subsignal("we_n", Pins("A18"), IOStandard("SSTL135")),
IOStandard("SSTL15")),
Subsignal("ba", Pins("B17 D18 A17"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("A19"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("B19"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("A18"), IOStandard("SSTL15")),
# cs_n is hardwired on the board
#Subsignal("cs_n", Pins(""), IOStandard("SSTL135")),
Subsignal("dm", Pins("A22 C22"), IOStandard("SSTL135")),
#Subsignal("cs_n", Pins(""), IOStandard("SSTL15")),
Subsignal("dm", Pins("A22 C22"), IOStandard("SSTL15")),
Subsignal("dq", Pins(
"D21 C21 B22 B21 D19 E20 C19 D20 C23 D23 B24 B25 C24 C26 A25 B26"),
IOStandard("SSTL135"),
IOStandard("SSTL15"),
Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("dqs_p", Pins("B20 A23"),
IOStandard("DIFF_SSTL135"),
IOStandard("DIFF_SSTL15"),
Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("dqs_n", Pins("A20 A24"),
IOStandard("DIFF_SSTL135"),
IOStandard("DIFF_SSTL15"),
Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("clk_p", Pins("F18"), IOStandard("DIFF_SSTL135")),
Subsignal("clk_n", Pins("F19"), IOStandard("DIFF_SSTL135")),
Subsignal("cke", Pins("E18"), IOStandard("SSTL135")),
Subsignal("odt", Pins("G19"), IOStandard("SSTL135")),
Subsignal("reset_n", Pins("H17"), IOStandard("SSTL135")),
Subsignal("clk_p", Pins("F18"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_n", Pins("F19"), IOStandard("DIFF_SSTL15")),
Subsignal("cke", Pins("E18"), IOStandard("SSTL15")),
Subsignal("odt", Pins("G19"), IOStandard("SSTL15")),
Subsignal("reset_n", Pins("H17"), IOStandard("SSTL15")),
Misc("SLEW=FAST"),
),
]