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sipeed_tang_primer_20k: Fix DDR3 module, SoC reset and remove DDR3 debug code. 

Now passing memtest with valid reported memory size:

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 BIOS CRC passed (d32a9529)

 LiteX git sha1: 85dadb82

--=============== SoC ==================--
CPU:		VexRiscv SMP-LINUX @ 48MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		64.0KiB
SRAM:		6.0KiB
L2:		512B
SDRAM:		128.0MiB 16-bit @ 192MT/s (CL-6 CWL-5)
MAIN-RAM:	128.0MiB

--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Read leveling:
  m0, b00: |00000000| delays: -
  m0, b01: |00000000| delays: -
  m0, b02: |01100000| delays: 01+-00
  m0, b03: |00000000| delays: -
  best: m0, b02 delays: 01+-00
  m1, b00: |00000000| delays: -
  m1, b01: |00000000| delays: -
  m1, b02: |01100000| delays: 01+-00
  m1, b03: |00000000| delays: -
  best: m1, b02 delays: 01+-00
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
  Write: 0x40000000-0x40200000 2.0MiB
   Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
  Write speed: 11.7MiB/s
   Read speed: 17.4MiB/s
This commit is contained in:
Florent Kermarrec 2023-08-29 16:50:17 +02:00
parent 4862d0667c
commit 347b477b07
1 changed files with 6 additions and 24 deletions
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30
litex_boards/targets/sipeed_tang_primer_20k.py
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@ -25,7 +25,7 @@ from liteeth.phy.rmii import LiteEthPHYRMII
from litex_boards.platforms import sipeed_tang_primer_20k from litex_boards.platforms import sipeed_tang_primer_20k
from litedram.common import PHYPadsReducer from litedram.common import PHYPadsReducer
from litedram.modules import MT41J128M16 from litedram.modules import MT41K64M16
from litedram.phy import GW2DDRPHY from litedram.phy import GW2DDRPHY
# CRG ---------------------------------------------------------------------------------------------- # CRG ----------------------------------------------------------------------------------------------
@ -56,7 +56,7 @@ class _CRG(LiteXModule):
# PLL # PLL
self.pll = pll = GW2APLL(devicename=platform.devicename, device=platform.device) self.pll = pll = GW2APLL(devicename=platform.devicename, device=platform.device)
self.comb += pll.reset.eq(~por_done | self.rst) self.comb += pll.reset.eq(~por_done)
pll.register_clkin(clk27, 27e6) pll.register_clkin(clk27, 27e6)
pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq) pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
self.specials += [ self.specials += [
@ -70,7 +70,7 @@ class _CRG(LiteXModule):
i_HCLKIN = self.cd_sys2x.clk, i_HCLKIN = self.cd_sys2x.clk,
i_RESETN = ~self.reset, i_RESETN = ~self.reset,
o_CLKOUT = self.cd_sys.clk), o_CLKOUT = self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset), AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.rst | self.reset),
] ]
# Init clock domain # Init clock domain
@ -122,10 +122,9 @@ class BaseSoC(SoCCore):
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Tang Primer 20K", **kwargs) SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Tang Primer 20K", **kwargs)
# DDR3 SDRAM ------------------------------------------------------------------------------- # DDR3 SDRAM -------------------------------------------------------------------------------
# FIXME: WIP / Untested.
if not self.integrated_main_ram_size: if not self.integrated_main_ram_size:
self.ddrphy = GW2DDRPHY( self.ddrphy = GW2DDRPHY(
pads = PHYPadsReducer(platform.request("ddram"), [0, 1]), pads = platform.request("ddram"),
sys_clk_freq = sys_clk_freq sys_clk_freq = sys_clk_freq
) )
self.ddrphy.settings.rtt_nom = "disabled" self.ddrphy.settings.rtt_nom = "disabled"
@ -133,25 +132,8 @@ class BaseSoC(SoCCore):
self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MT41J128M16(sys_clk_freq, "1:2"), module = MT41K64M16(sys_clk_freq, "1:2"),
l2_cache_size = 0 l2_cache_size = kwargs.get("l2_size", 8192)
)
# ./sipeed_tang_primer_20k.py --cpu-variant=lite --uart-name=crossover+uartbone --csr-csv=csr.csv --build --load
# litex_server --uart --uart-port=/dev/ttyUSB2
# litex_term crossover
# litescope_cli
if kwargs["uart_name"] == "crossover+uartbone":
from litescope import LiteScopeAnalyzer
analyzer_signals = [
self.ddrphy.dfi.p0,
self.ddrphy.dfi.p0.wrdata_en,
self.ddrphy.dfi.p1.rddata_en,
]
self.analyzer = LiteScopeAnalyzer(analyzer_signals,
depth = 128,
clock_domain = "sys",
samplerate = sys_clk_freq,
csr_csv = "analyzer.csv"
) )
# SPI Flash -------------------------------------------------------------------------------- # SPI Flash --------------------------------------------------------------------------------