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Merge pull request #303 from sergachev/master 

sipeed_tang_nano_4k: add option to build with Gowin EMCU
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enjoy-digital 2021-12-09 14:30:54 +01:00 committed by GitHub
parent 6f9e61360c 14a8c50e97
commit 35e0026875
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 25 additions and 13 deletions
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38
litex_boards/targets/sipeed_tang_nano_4k.py
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@ -64,16 +64,18 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
def __init__(self, sys_clk_freq=int(27e6), with_hyperram=False, with_led_chaser=True, with_video_terminal=True, **kwargs): def __init__(self, sys_clk_freq=int(27e6), with_hyperram=False, with_led_chaser=True, with_video_terminal=True, **kwargs):
platform = tang_nano_4k.Platform() platform = tang_nano_4k.Platform()
# Put BIOS in SPIFlash to save BlockRAMs. if 'cpu_type' in kwargs and kwargs['cpu_type'] == 'gowin_emcu':
kwargs["integrated_rom_size"] = 0 kwargs['with_uart'] = False # CPU has own UART
kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + 0 kwargs['integrated_sram_size'] = 0 # SRAM is directly attached to CPU
kwargs["integrated_rom_size"] = 0 # boot flash directly attached to CPU
kwargs["cpu_type"] = 'vexriscv' else:
kwargs["cpu_variant"] = 'minimal' # Put BIOS in SPIFlash to save BlockRAMs.
self.mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
kwargs["integrated_rom_size"] = 0
kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + 0
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, SoCCore.__init__(self, platform, sys_clk_freq,
@ -81,6 +83,9 @@ class BaseSoC(SoCCore):
ident_version = True, ident_version = True,
**kwargs) **kwargs)
if self.cpu_type == 'vexriscv':
assert self.cpu_variant == 'minimal', 'use --cpu-variant=minimal to fit into number of BSRAMs'
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, with_video_pll=with_video_terminal) self.submodules.crg = _CRG(platform, sys_clk_freq, with_video_pll=with_video_terminal)
@ -89,12 +94,15 @@ class BaseSoC(SoCCore):
from litespi.opcodes import SpiNorFlashOpCodes as Codes from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="1x", module=W25Q32(Codes.READ_1_1_1), with_master=False) self.add_spi_flash(mode="1x", module=W25Q32(Codes.READ_1_1_1), with_master=False)
if self.cpu_type == 'gowin_emcu':
self.cpu.connect_uart(platform.request('serial'))
else:
# Add ROM linker region -------------------------------------------------------------------- # Add ROM linker region --------------------------------------------------------------------
self.bus.add_region("rom", SoCRegion( self.bus.add_region("rom", SoCRegion(
origin = self.mem_map["spiflash"] + 0, origin = self.mem_map["spiflash"] + 0,
size = 64*kB, size = 64*kB,
linker = True) linker = True)
) )
# HyperRAM --------------------------------------------------------------------------------- # HyperRAM ---------------------------------------------------------------------------------
if with_hyperram: if with_hyperram:
@ -136,8 +144,12 @@ def main():
soc_core_args(parser) soc_core_args(parser)
args = parser.parse_args() args = parser.parse_args()
if args.cpu_type == 'gowin_emcu':
# FIXME: ARM software not supported yet
args.no_compile_software = True
soc = BaseSoC( soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)), sys_clk_freq=int(float(args.sys_clk_freq)),
**soc_core_argdict(args) **soc_core_argdict(args)
) )