efinix_xyloni_dev_kit: Only force variant to minimal for Vexriscv.

2021-10-22 14:47:12 +02:00 · 2021-10-22 14:47:12 +02:00 · 394ea23b99
parent 75fd276dbe
commit 394ea23b99
1 changed files with 2 additions and 1 deletions
--- a/litex_boards/targets/efinix_xyloni_dev_kit.py
+++ b/litex_boards/targets/efinix_xyloni_dev_kit.py
@ -56,7 +56,8 @@ class BaseSoC(SoCCore):
        kwargs["integrated_rom_size"]  = 0

        # Set CPU variant / reset address
-        kwargs["cpu_variant"]       = "minimal"
+        if kwargs.get("cpu_type", "vexriscv") == "vexriscv":
+            kwargs["cpu_variant"] = "minimal"
        kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset

        # SoCCore ----------------------------------------------------------------------------------