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add de10 nano board 

add iostandard to hdmi
This commit is contained in:
Paul Sajna 2020-01-25 03:00:57 -08:00
parent 2ec6bc0bdc
commit 3a6a9258ce
2 changed files with 194 additions and 0 deletions
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100
litex_boards/community/platforms/de10nano.py Normal file
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# This file is Copyright (c) 2014-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster
# IOs ----------------------------------------------------------------------------------------------
_io = [
("clk50", 0, Pins("V11"), IOStandard("3.3-V LVTTL")),
("clk50", 1, Pins("Y13"), IOStandard("3.3-V LVTTL")),
("clk50", 2, Pins("E11"), IOStandard("3.3-V LVTTL")),
("user_led", 0, Pins("W15"), IOStandard("3.3-V LVTTL")),
("user_led", 1, Pins("AA24"), IOStandard("3.3-V LVTTL")),
("user_led", 2, Pins("V16"), IOStandard("3.3-V LVTTL")),
("user_led", 3, Pins("V15"), IOStandard("3.3-V LVTTL")),
("user_led", 4, Pins("AF26"), IOStandard("3.3-V LVTTL")),
("user_led", 5, Pins("AE26"), IOStandard("3.3-V LVTTL")),
("key", 0, Pins("AH17"), IOStandard("3.3-V LVTTL")),
("key", 1, Pins("AH16"), IOStandard("3.3-V LVTTL")),
("sw", 0, Pins("Y24"), IOStandard("3.3-V LVTTL")),
("sw", 1, Pins("W24"), IOStandard("3.3-V LVTTL")),
("sw", 2, Pins("W21"), IOStandard("3.3-V LVTTL")),
("sw", 3, Pins("W20"), IOStandard("3.3-V LVTTL")),
("serial", 0,
Subsignal("tx", Pins("AF13"), IOStandard("3.3-V LVTTL")), # Arduino_IO1
Subsignal("rx", Pins("AG13"), IOStandard("3.3-V LVTTL")) # Arduino_IO0
),
("g_sensor", 0,
Subsignal("int", Pins("A17")),
Subsignal("sclk", Pins("C18")),
Subsignal("sdat", Pins("A19")),
IOStandard("3.3-V LVTTL")
),
("adc", 0,
Subsignal("convst", Pins("U9")),
Subsignal("sclk", Pins("V10")),
Subsignal("sdi", Pins("AC4")),
Subsignal("sdo", Pins("AD4")),
IOStandard("3.3-V LVTTL")
),
("hdmi", 0,
Subsignal("tx_d_r", Pins("AS12 AE12 W8 Y8 AD11 AD10 AE11 Y5")),
Subsignal("tx_d_g", Pins("AF10 Y4 AE9 AB4 AE7 AF6 AF8 AF5")),
Subsignal("tx_d_b", Pins("AE4 AH2 AH4 AH5 AH6 AG6 AF9 AE8")),
Subsignal("tx_clk", Pins("AG5")),
Subsignal("tx_de", Pins("AD19")),
Subsignal("tx_hs", Pins("T8")),
Subsignal("tx_vs", Pins("V13")),
Subsignal("tx_int", Pins("AF11")),
Subsignal("i2s0", Pins("T13")),
Subsignal("mclk", Pins("U11")),
Subsignal("lrclk", Pins("T11")),
Subsignal("sclk", Pins("T12")),
Subsignal("scl", Pins("U10")),
Subsignal("sda", Pins("AA4")),
IOStandard("3.3-V LVTTL")
),
("gpio_0", 0,
Pins("V12 E8 W12 D11 D8 AH13 AF7 AH14 AF4 AH3 AD5 AG14 AE23 D12 AD20",
"C12 AD17 AC23 AC22 Y19 AB23 AA19 W11 AA18 W14 Y18 Y17 AB25 AB26",
"Y11 AA26 AA13 AA11"),
IOStandard("3.3-V LVTTL")
),
("gpio_1", 0,
Pins("Y15 AC24 AA15 AD26 AG28 AF28 AE25 AF27 AG26 AH27 AG25 AH26 AH24",
"AF25 AG23 AF24 AG24 AH22 AH21 AG21 AH23 AA20 AF22 AE22 AG20 AF21",
"AH23 AA20 AF22 AE22 AG20 AF21 AG19 AH19 AG18 AH18 AF18 AF20 AG15",
"AE20 AE19 AE17"),
IOStandard("3.3-V LVTTL")
),
("arduino", 0,
Pins("AG13 AF13 AG10 AG9 U14 U13 AG8 AH8 AF17 AE15 AF15 AG16 AH11 AH12",
"AH9, AG11, AH7"),
IOStandard("3.3-V LVTTL")
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(AlteraPlatform):
default_clk_name = "clk50"
default_clk_period = 1e9/50e6
def __init__(self):
AlteraPlatform.__init__(self, "5CSEBA6U23I7", _io)
def create_programmer(self):
return USBBlaster()

94
litex_boards/community/targets/de10nano.py Executable file
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#!/usr/bin/env python3
# This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
import argparse
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import de10nano
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain()
# # #
# Clk / Rst
clk50 = platform.request("clk50")
platform.add_period_constraint(clk50, 1e9/50e6)
# PLL
pll_locked = Signal()
pll_clk_out = Signal(6)
self.specials += \
Instance("ALTPLL",
p_BANDWIDTH_TYPE = "AUTO",
p_CLK0_DIVIDE_BY = 1,
p_CLK0_DUTY_CYCLE = 50,
p_CLK0_MULTIPLY_BY = 1,
p_CLK0_PHASE_SHIFT = "0",
p_CLK1_DIVIDE_BY = 1,
p_CLK1_DUTY_CYCLE = 50,
p_CLK1_MULTIPLY_BY = 1,
p_CLK1_PHASE_SHIFT = "-10000",
p_COMPENSATE_CLOCK = "CLK0",
p_INCLK0_INPUT_FREQUENCY = 20000,
p_OPERATION_MODE = "NORMAL",
i_INCLK = clk50,
o_CLK = pll_clk_out,
i_ARESET = 0,
i_CLKENA = 0x3f,
i_EXTCLKENA = 0xf,
i_FBIN = 1,
i_PFDENA = 1,
i_PLLENA = 1,
o_LOCKED = pll_locked,
)
self.comb += [
self.cd_sys.clk.eq(pll_clk_out[0]),
self.cd_sys_ps.clk.eq(pll_clk_out[1]),
]
self.specials += [
AsyncResetSynchronizer(self.cd_sys, ~pll_locked),
AsyncResetSynchronizer(self.cd_sys_ps, ~pll_locked)
]
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(50e6), **kwargs):
assert sys_clk_freq == int(50e6)
platform = de10nano.Platform()
# SoCSDRAM ---------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform)
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on DE10 Nano")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()
if __name__ == "__main__":
main()