Add qmtech Cyclone IV Starter Kit
This commit is contained in:
Franck Jullien
parent
e6762e228c
commit
3ec18c3583
|
|
@ -0,0 +1,165 @@
|
|||
#
|
||||
# This file is part of LiteX-Boards.
|
||||
#
|
||||
# Copyright (c) 2022 Franck Jullien <franck.jullien@gmail.com>
|
||||
# SPDX-License-Identifier: BSD-2-Clause
|
||||
|
||||
from litex.build.generic_platform import *
|
||||
from litex.build.altera import AlteraPlatform
|
||||
from litex.build.altera.programmer import USBBlaster
|
||||
|
||||
# IOs ----------------------------------------------------------------------------------------------
|
||||
|
||||
_io = [
|
||||
# Clk
|
||||
("clk50", 0, Pins("T2"), IOStandard("3.3-V LVTTL")),
|
||||
|
||||
# LED
|
||||
("led", 0, Pins("E3"), IOStandard("3.3-V LVTTL")),
|
||||
|
||||
# Button
|
||||
("key", 0, Pins("J4"), IOStandard("3.3-V LVTTL")),
|
||||
|
||||
("serial", 0,
|
||||
Subsignal("tx", Pins("Y22"), IOStandard("3.3-V LVTTL")),
|
||||
Subsignal("rx", Pins("Y21"), IOStandard("3.3-V LVTTL"))
|
||||
),
|
||||
|
||||
# 7-segments display
|
||||
("seven_seg_ctl", 0,
|
||||
Subsignal("dig", Pins("Y13 W13 V13")),
|
||||
Subsignal("segments", Pins("V15 U20 W20 Y17 W15 W17 U19")),
|
||||
Subsignal("dot", Pins("W19")),
|
||||
IOStandard("3.3-V LVTTL")
|
||||
),
|
||||
|
||||
# VGA
|
||||
("vga", 0,
|
||||
Subsignal("hsync_n", Pins("AA13")),
|
||||
Subsignal("vsync_n", Pins("AB10")),
|
||||
Subsignal("r", Pins("AB19 AA19 AB20 AA20 AA21")),
|
||||
Subsignal("g", Pins("AB16 AA16 AB17 AA17 AA18 AB18")),
|
||||
Subsignal("b", Pins("AA14 AB13 AA15 AB14 AB15")),
|
||||
IOStandard("3.3-V LVTTL")
|
||||
),
|
||||
|
||||
# SPIFlash (W25Q64)
|
||||
("spiflash", 0,
|
||||
# clk
|
||||
Subsignal("cs_n", Pins("E2")),
|
||||
Subsignal("clk", Pins("K2")),
|
||||
Subsignal("mosi", Pins("D1")),
|
||||
Subsignal("miso", Pins("E2")),
|
||||
IOStandard("3.3-V LVTTL"),
|
||||
),
|
||||
|
||||
# SDR SDRAM
|
||||
("sdram_clock", 0, Pins("Y6"), IOStandard("3.3-V LVTTL")),
|
||||
("sdram", 0,
|
||||
Subsignal("a", Pins(
|
||||
"V2 V1 U2 U1 V3 V4 Y2 AA1",
|
||||
"Y3 V5 W1 Y4 V6")),
|
||||
Subsignal("ba", Pins("Y1 W2")),
|
||||
Subsignal("cs_n", Pins("AA3")),
|
||||
Subsignal("cke", Pins("W6")),
|
||||
Subsignal("ras_n", Pins("AB3")),
|
||||
Subsignal("cas_n", Pins("AA4")),
|
||||
Subsignal("we_n", Pins("AB4")),
|
||||
Subsignal("dq", Pins(
|
||||
"AA10 AB9 AA9 AB8 AA8 AB7 AA7 AB5",
|
||||
"Y7 W8 Y8 V9 V10 Y10 W10 V11")),
|
||||
Subsignal("dm", Pins("AA5 W7")),
|
||||
IOStandard("3.3-V LVTTL")
|
||||
),
|
||||
|
||||
# GMII Ethernet
|
||||
("eth_clocks", 0,
|
||||
Subsignal("tx", Pins("R22")),
|
||||
Subsignal("gtx", Pins("L21")),
|
||||
Subsignal("rx", Pins("F21")),
|
||||
IOStandard("3.3-V LVTTL")
|
||||
),
|
||||
("eth", 0,
|
||||
Subsignal("rst_n", Pins("N22")),
|
||||
Subsignal("mdio", Pins("W21")),
|
||||
Subsignal("mdc", Pins("W22")),
|
||||
Subsignal("rx_dv", Pins("D22")),
|
||||
Subsignal("rx_er", Pins("K22")),
|
||||
Subsignal("rx_data", Pins("D21 E22 E21 F22 H22 H21 J22 J21")),
|
||||
Subsignal("tx_en", Pins("M22")),
|
||||
Subsignal("tx_er", Pins("V21")),
|
||||
Subsignal("tx_data", Pins("M21 N21 P22 P21 R21 U22 U21 V22")),
|
||||
Subsignal("col", Pins("K21")),
|
||||
Subsignal("crs", Pins("L22")),
|
||||
IOStandard("3.3-V LVTTL")
|
||||
),
|
||||
]
|
||||
|
||||
_connectors = [
|
||||
("J11", {
|
||||
1: "R1", 7: "R2",
|
||||
2: "P1", 8: "P2",
|
||||
3: "N1", 9: "N2",
|
||||
4: "M1", 10: "M2",
|
||||
5: "-" , 11: "-",
|
||||
6: "-" , 12: "-",
|
||||
}),
|
||||
("J10", {
|
||||
1: "J1", 7: "J2",
|
||||
2: "H1", 8: "H2",
|
||||
3: "F1", 9: "F2",
|
||||
4: "E1", 10: "D2",
|
||||
5: "-" , 11: "-",
|
||||
6: "-" , 12: "-",
|
||||
}),
|
||||
("JP1", {
|
||||
1: "-", 2: "-",
|
||||
3: "A8", 4: "B8",
|
||||
5: "A7", 6: "B7",
|
||||
7: "A6", 8: "B6",
|
||||
9: "A5", 10: "B5",
|
||||
11: "A4", 12: "B4",
|
||||
13: "A3", 14: "B3",
|
||||
15: "B1", 16: "B2",
|
||||
17: "C1", 18: "C2",
|
||||
}),
|
||||
("J12", {
|
||||
1: "-", 2: "-",
|
||||
3: "C22", 4: "C21",
|
||||
5: "B22", 6: "B21",
|
||||
7: "H20", 8: "H19",
|
||||
9: "F20", 10: "F19",
|
||||
11: "C20", 12: "D20",
|
||||
13: "C19", 14: "D19",
|
||||
15: "C17", 16: "D17",
|
||||
17: "A20", 18: "B20",
|
||||
19: "A19", 20: "B19",
|
||||
21: "A18", 22: "B18",
|
||||
23: "A17", 24: "B17",
|
||||
25: "A16", 26: "B16",
|
||||
27: "A15", 28: "B15",
|
||||
29: "A14", 30: "B14",
|
||||
31: "A13", 32: "B13",
|
||||
33: "A10", 34: "B10",
|
||||
35: "A9", 36: "B9",
|
||||
37: "-", 38: "-",
|
||||
39: "-", 40: "-",
|
||||
})
|
||||
]
|
||||
|
||||
# Platform -----------------------------------------------------------------------------------------
|
||||
|
||||
class Platform(AlteraPlatform):
|
||||
default_clk_name = "clk50"
|
||||
default_clk_period = 1e9/50e6
|
||||
|
||||
def __init__(self, toolchain="quartus"):
|
||||
AlteraPlatform.__init__(self, "EP4CE15F23C8", _io, _connectors, toolchain=toolchain)
|
||||
self.add_platform_command("set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION \"USE AS REGULAR IO\"")
|
||||
|
||||
def create_programmer(self):
|
||||
return USBBlaster()
|
||||
|
||||
def do_finalize(self, fragment):
|
||||
AlteraPlatform.do_finalize(self, fragment)
|
||||
self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
|
||||
|
|
@ -0,0 +1,135 @@
|
|||
#!/usr/bin/env python3
|
||||
|
||||
#
|
||||
# This file is part of LiteX-Boards.
|
||||
#
|
||||
# Copyright (c) 2022 Franck Jullien <franck.jullien@collshade.fr>
|
||||
# SPDX-License-Identifier: BSD-2-Clause
|
||||
|
||||
from migen import *
|
||||
from migen.genlib.resetsync import AsyncResetSynchronizer
|
||||
|
||||
from litex.build.io import DDROutput
|
||||
|
||||
from litex_boards.platforms import qmtech_ep4ce15_starter_kit
|
||||
|
||||
from litex.soc.cores.clock import CycloneIVPLL
|
||||
from litex.soc.integration.soc_core import *
|
||||
from litex.soc.integration.builder import *
|
||||
|
||||
from litex.soc.cores.led import LedChaser
|
||||
|
||||
from litedram.modules import W9825G6KH6
|
||||
from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
|
||||
|
||||
# CRG ----------------------------------------------------------------------------------------------
|
||||
|
||||
class _CRG(Module):
|
||||
def __init__(self, platform, sys_clk_freq, sdram_rate="1:1"):
|
||||
self.rst = Signal()
|
||||
self.clock_domains.cd_sys = ClockDomain()
|
||||
if sdram_rate == "1:2":
|
||||
self.clock_domains.cd_sys2x = ClockDomain()
|
||||
self.clock_domains.cd_sys2x_ps = ClockDomain()
|
||||
else:
|
||||
self.clock_domains.cd_sys_ps = ClockDomain()
|
||||
|
||||
# # #
|
||||
|
||||
# Clk / Rst
|
||||
clk50 = platform.request("clk50")
|
||||
|
||||
# PLL
|
||||
self.submodules.pll = pll = CycloneIVPLL(speedgrade="-6")
|
||||
self.comb += pll.reset.eq(self.rst)
|
||||
pll.register_clkin(clk50, 50e6)
|
||||
pll.create_clkout(self.cd_sys, sys_clk_freq)
|
||||
if sdram_rate == "1:2":
|
||||
pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
|
||||
# theoretically 90 degrees, but increase to relax timing
|
||||
pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180)
|
||||
else:
|
||||
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
|
||||
|
||||
# SDRAM clock
|
||||
sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
|
||||
self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
|
||||
|
||||
# BaseSoC ------------------------------------------------------------------------------------------
|
||||
|
||||
class BaseSoC(SoCCore):
|
||||
def __init__(self, sys_clk_freq=int(50e6), with_jtaguart=False, with_jtagbone=False,
|
||||
with_led_chaser=True, sdram_rate="1:1", **kwargs):
|
||||
platform = qmtech_ep4ce15_starter_kit.Platform()
|
||||
|
||||
# CRG --------------------------------------------------------------------------------------
|
||||
self.submodules.crg = _CRG(platform, sys_clk_freq, sdram_rate = sdram_rate)
|
||||
|
||||
# SoCCore ----------------------------------------------------------------------------------
|
||||
if with_jtagbone:
|
||||
kwargs["uart_name"] = "crossover"
|
||||
if with_jtaguart:
|
||||
kwargs["uart_name"] = "jtag_uart"
|
||||
|
||||
SoCCore.__init__(self, platform, sys_clk_freq,
|
||||
ident = "LiteX SoC on QMTECH Cyclone IV Starter Kit",
|
||||
**kwargs
|
||||
)
|
||||
|
||||
# JTAGbone ---------------------------------------------------------------------------------
|
||||
if with_jtagbone:
|
||||
self.add_jtagbone()
|
||||
|
||||
# SDR SDRAM --------------------------------------------------------------------------------
|
||||
if not self.integrated_main_ram_size:
|
||||
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
|
||||
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
|
||||
self.add_sdram("sdram",
|
||||
phy = self.sdrphy,
|
||||
module = W9825G6KH6(sys_clk_freq, sdram_rate),
|
||||
l2_cache_size = kwargs.get("l2_size", 8192)
|
||||
)
|
||||
|
||||
# Leds -------------------------------------------------------------------------------------
|
||||
if with_led_chaser:
|
||||
seven_seg_display = platform.request("seven_seg_ctl")
|
||||
self.comb += seven_seg_display.dig.eq(0b111)
|
||||
self.submodules.leds = LedChaser(
|
||||
pads = seven_seg_display.segments,
|
||||
sys_clk_freq = sys_clk_freq)
|
||||
|
||||
# Build --------------------------------------------------------------------------------------------
|
||||
|
||||
def main():
|
||||
from litex.soc.integration.soc import LiteXSoCArgumentParser
|
||||
parser = LiteXSoCArgumentParser(description="LiteX SoC on QMTECH EP4CE15")
|
||||
target_group = parser.add_argument_group(title="Target options")
|
||||
target_group.add_argument("--build", action="store_true", help="Build design.")
|
||||
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
|
||||
target_group.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
|
||||
target_group.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
|
||||
target_group.add_argument("--with-jtaguart", action="store_true", help="Enable JTAGUart support.")
|
||||
target_group.add_argument("--with-jtagbone", action="store_true", help="Enable JTAGbone support.")
|
||||
|
||||
builder_args(parser)
|
||||
soc_core_args(parser)
|
||||
args = parser.parse_args()
|
||||
|
||||
soc = BaseSoC(
|
||||
sys_clk_freq = int(float(args.sys_clk_freq)),
|
||||
sdram_rate = args.sdram_rate,
|
||||
with_jtagbone = args.with_jtagbone,
|
||||
with_jtaguart = args.with_jtaguart,
|
||||
**soc_core_argdict(args)
|
||||
)
|
||||
|
||||
builder = Builder(soc, **builder_argdict(args))
|
||||
if args.build:
|
||||
builder.build()
|
||||
|
||||
if args.load:
|
||||
prog = soc.platform.create_programmer()
|
||||
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
Loading…
Reference in New Issue