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digilent_arty_s7: Add SPI Flash.

This commit is contained in:
Florent Kermarrec 2021-07-28 14:22:26 +02:00
parent 64eadd8012
commit 401568c54e
1 changed files with 15 additions and 7 deletions
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10
litex_boards/targets/digilent_arty_s7.py
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@ -51,7 +51,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, variant="s7-50", sys_clk_freq=int(100e6), with_led_chaser=True, **kwargs):
def __init__(self, variant="s7-50", sys_clk_freq=int(100e6), with_spi_flash=False, with_led_chaser=True, **kwargs):
platform = arty_s7.Platform(variant=variant)
# SoCCore ----------------------------------------------------------------------------------
@ -75,6 +75,12 @@ class BaseSoC(SoCCore):
l2_cache_size = kwargs.get("l2_size", 8192)
)
# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:
from litespi.modules import S25FL128S
from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="4x", module=S25FL128S(Codes.READ_1_1_4), with_master=True)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
@ -89,6 +95,7 @@ def main():
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--variant", default="s7-50", help="Board variant: s7-50 (default) or s7-25")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)")
parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed)")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
@ -97,6 +104,7 @@ def main():
soc = BaseSoC(
variant = args.variant,
sys_clk_freq = int(float(args.sys_clk_freq)),
with_spi_flash = args.with_spi_flash,
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))