Merge pull request #526 from Chandler-Kluser/master
Added QMTECH RP2040 Daughterboard
This commit is contained in:
enjoy-digital
GitHub
commit
41351a845a
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@ -141,7 +141,7 @@ class Platform(Xilinx7SeriesPlatform):
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default_clk_period = 1e9/50e6
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default_clk_period = 1e9/50e6
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kgates = None
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kgates = None
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def __init__(self, kgates=100, toolchain="vivado", with_daughterboard=False):
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def __init__(self, kgates=100, toolchain="vivado", with_daughterboard=False, with_rp2040_daughterboard=False):
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assert(kgates in [75, 100], "kgates can only be 75 or 100 representing a XC7A75T, XC7TA100T")
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assert(kgates in [75, 100], "kgates can only be 75 or 100 representing a XC7A75T, XC7TA100T")
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self.kgates = kgates
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self.kgates = kgates
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device = f"xc7a{kgates}tfgg676-1"
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device = f"xc7a{kgates}tfgg676-1"
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@ -160,6 +160,12 @@ class Platform(Xilinx7SeriesPlatform):
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io += daughterboard.io
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io += daughterboard.io
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connectors += daughterboard.connectors
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connectors += daughterboard.connectors
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if with_rp2040_daughterboard:
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from litex_boards.platforms.qmtech_rp2040_daughterboard import QMTechDaughterboard
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daughterboard = QMTechDaughterboard(IOStandard("LVCMOS33"))
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io += daughterboard.io
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connectors += daughterboard.connectors
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Xilinx7SeriesPlatform.__init__(self, device, io, connectors, toolchain=toolchain)
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Xilinx7SeriesPlatform.__init__(self, device, io, connectors, toolchain=toolchain)
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self.toolchain.bitstream_commands = \
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
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@ -179,4 +185,4 @@ class Platform(Xilinx7SeriesPlatform):
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def do_finalize(self, fragment):
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def do_finalize(self, fragment):
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Xilinx7SeriesPlatform.do_finalize(self, fragment)
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Xilinx7SeriesPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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@ -0,0 +1,136 @@
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2023 Kazumoto Kojima
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# Copyright (c) 2023 Hans Baier <hansfbaier@gmail.com>
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# Copyright (c) 2023 Chandler Klüser <chandler.kluser@gmail.com>
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#
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import Subsignal, Pins, IOStandard, Misc
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class QMTechDaughterboard:
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"""
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the QMTech daughterboard contains standard peripherals
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and can be used with a number of different FPGA core boards
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source: https://www.aliexpress.com/item/1005005094654777.html
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"""
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def __init__(self, io_standard) -> None:
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"""
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because the board can be used with FPGAs core boards from
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different vendors, the constructor needs the vendor specific IOStandard
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"""
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self.io = [
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# GMII Ethernet
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("eth_clocks", 0,
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Subsignal("tx", Pins("J3:22")),
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Subsignal("gtx", Pins("J3:29")),
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Subsignal("rx", Pins("J3:37")),
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io_standard
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),
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("eth", 0,
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# rst is hardwired on the board
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#Subsignal("rst_n", Pins("-")),
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Subsignal("int_n", Pins("J3:26")),
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Subsignal("mdio", Pins("J3:15")),
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Subsignal("mdc", Pins("J3:16")),
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Subsignal("rx_dv", Pins("J3:42")),
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Subsignal("rx_er", Pins("J3:32")),
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Subsignal("rx_data", Pins("J3:41 J3:40 J3:39 J3:38 J3:36 J3:35 J3:34 J3:33")),
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Subsignal("tx_en", Pins("J3:28")),
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Subsignal("tx_er", Pins("J3:17")),
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Subsignal("tx_data", Pins("J3:27 J3:25 J3:24 J3:23 J3:21 J3:20 J3:19 J3:18")),
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Subsignal("col", Pins("J3:31")),
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Subsignal("crs", Pins("J3:30")),
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io_standard
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),
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# VGA
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("vga", 0,
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Subsignal("hsync_n", Pins("J3:44")),
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Subsignal("vsync_n", Pins("J3:43")),
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Subsignal("r", Pins("J3:57 J3:56 J3:59 J3:58 J3:60")),
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Subsignal("g", Pins("J3:51 J3:50 J3:53 J3:52 J3:54 J3:55")),
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Subsignal("b", Pins("J3:46 J3:45 J3:48 J3:47 J3:49")),
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io_standard
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),
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# PullUp resistors are on the board, so we don't need them in the FPGA
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("sdcard", 0,
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Subsignal("data", Pins("J3:10 J3:9 J3:14 J3:13")),
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Subsignal("cmd", Pins("J3:12")),
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Subsignal("clk", Pins("J3:11")),
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# RP2040 Daughterboard have CD pin pulled up
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# Subsignal("cd", Pins("Jx:x")),
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io_standard,
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),
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# RP2040 pins
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# Native RP2040 Firmware comes with a single 9600-8-N-1 USB to UART converter
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# GPIO28 is used as UART0 TX. GPIO29 is used as UART0 RX
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# Firmware and Source Code available at: https://github.com/ChinaQMTECH/DB_FPGA_with_RP2040
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("rp2040", 0,
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Subsignal( "gpio0", Pins("J3:7")),
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Subsignal( "gpio1", Pins("J3:8")),
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Subsignal( "gpio2", Pins("J2:44")),
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Subsignal( "gpio3", Pins("J2:43")),
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Subsignal( "gpio4", Pins("J2:42")),
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Subsignal( "gpio5", Pins("J2:41")),
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Subsignal( "gpio6", Pins("J2:40")),
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Subsignal( "gpio7", Pins("J2:39")),
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Subsignal( "gpio8", Pins("J2:38")),
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Subsignal( "gpio9", Pins("J2:37")),
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Subsignal( "gpio10", Pins("J2:36")),
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Subsignal( "gpio11", Pins("J2:35")),
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Subsignal( "gpio12", Pins("J2:34")),
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Subsignal( "gpio13", Pins("J2:33")),
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Subsignal( "gpio14", Pins("J2:32")),
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Subsignal( "gpio15", Pins("J2:31")),
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# RP2040 GPIOs 16 to 19 are external headers
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# They can be used to drive JTAG interface using Dirty Jtag (for RP2040)
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# More information at: https://github.com/phdussud/pico-dirtyJtag
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# A second option is to use the same pins to drive a
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# Xilinx Virtual Cable (XVC) client for JTAG Programming in Xilinx FPGAs Core Boards
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# More information at: https://github.com/kholia/xvc-pico
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# Subsignal( "gpio16", Pins("Jx:x")),
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# Subsignal( "gpio17", Pins("Jx:x")),
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# Subsignal( "gpio18", Pins("Jx:x")),
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# Subsignal( "gpio19", Pins("Jx:x")),
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Subsignal( "gpio20", Pins("J2:30")),
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Subsignal( "gpio21", Pins("J2:29")),
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Subsignal( "gpio22", Pins("J2:28")),
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Subsignal( "gpio23", Pins("J2:27")),
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# RP2040 GPIOs 24 and 25 are connected to User Push Button and User LED
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# Subsignal( "gpio24", Pins("Jx:x")),
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# Subsignal( "gpio25", Pins("Jx:x")),
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Subsignal("gpio26_adc0", Pins("J2:26")),
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Subsignal("gpio27_adc1", Pins("J2:25")),
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Subsignal("gpio28_adc2", Pins("J2:16")),
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Subsignal("gpio29_adc3", Pins("J2:15")),
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io_standard,
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),
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]
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connectors = [
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("pmoda", "J2:17 J2:19 J2:21 J2:23 J2:18 J2:20 J2:22 J2:24"), #J10
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("pmodb", "J2:7 J2:9 J2:11 J2:13 J2:8 J2:10 J2:12 J2:14"), #J11
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("J1", {
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3: "J2:60",
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4: "J2:59",
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5: "J2:58",
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6: "J2:57",
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7: "J2:56",
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8: "J2:55",
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9: "J2:54",
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10: "J2:53",
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11: "J2:52",
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12: "J2:51",
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13: "J2:50",
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14: "J2:49",
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15: "J2:48",
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16: "J2:47",
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17: "J2:46",
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18: "J2:45"
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}),
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]
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