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init repo with litex official boards

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Florent Kermarrec 2019-06-10 17:09:51 +02:00
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README Normal file
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__ _ __ _ __ ___ __
/ / (_) /____ | |/_/___/ _ )___ ___ ________/ /__
/ /__/ / __/ -_)> </___/ _ / _ \/ _ `/ __/ _ (_-<
/____/_/\__/\__/_/|_| /____/\___/\_,_/_/ \_,_/___/
LiteX boards files
Copyright 2012-2019 / LiteX-Hub community
[> Intro
--------
Supported boards files (platforms/targets) for LiteX.
Official:
---------
Platforms / Targets actively tested and included in the CI system.
Partner:
-------
Platforms / Targets supported by other groups/partners.
Community:
----------
Platforms / Targets supported by the community in a "best effort" manner.

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litex_boards/__init__.py Normal file
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litex_boards/community/__init__.py Normal file
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litex_boards/official/__init__.py Normal file
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litex_boards/official/platforms/__init__.py Normal file
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litex_boards/official/platforms/ac701.py Normal file
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# This file is Copyright (c) 2019 Vamsi K Vytla <vamsi.vytla@gmail.com>
# License: BSD
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
("user_led", 0, Pins("M26"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("T24"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("T25"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("R26"), IOStandard("LVCMOS33")),
("cpu_reset", 0, Pins("U4"), IOStandard("SSTL15")),
("clk200", 0,
Subsignal("p", Pins("R3"), IOStandard("DIFF_SSTL15")),
Subsignal("n", Pins("P3"), IOStandard("DIFF_SSTL15"))
),
("clk156", 0,
Subsignal("p", Pins("M21"), IOStandard("LVDS_25")),
Subsignal("n", Pins("M22"), IOStandard("LVDS_25"))
),
("serial", 0,
Subsignal("cts", Pins("V19")),
Subsignal("rts", Pins("W19")),
Subsignal("tx", Pins("U19")),
Subsignal("rx", Pins("T19")),
IOStandard("LVCMOS18")
),
("eth_clocks", 0,
Subsignal("tx", Pins("U22")),
Subsignal("rx", Pins("U21")),
IOStandard("LVCMOS18")
),
("eth", 0,
Subsignal("rx_ctl", Pins("U14")),
Subsignal("rx_data", Pins("U17 V17 V16 V14")),
Subsignal("tx_ctl", Pins("T15")),
Subsignal("tx_data", Pins("U16 U15 T18 T17")),
Subsignal("rst_n", Pins("V18")),
Subsignal("mdc", Pins("W18")),
Subsignal("mdio", Pins("T14")),
IOStandard("LVCMOS18"), Misc("SLEW=FAST"), Drive(16)
),
("ddram", 0,
Subsignal("a", Pins(
"M4 J3 J1 L4 K5 M7 K1 M6",
"H1 K3 N7 L5 L7 N6 L3 K2"),
IOStandard("SSTL15")),
Subsignal("ba", Pins("N1 M1 H2"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("P1"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("T4"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("R1"), IOStandard("SSTL15")),
Subsignal("cs_n", Pins("T3"), IOStandard("SSTL15")),
Subsignal("dm", Pins("AC6 AC4 AA3 U7 G1 F3 G5 H9"),
IOStandard("SSTL15")),
Subsignal("dq", Pins(
"AB6 AA8 Y8 AB5 AA5 Y5 Y6 Y7",
"AF4 AF5 AF3 AE3 AD3 AC3 AB4 AA4",
"AC2 AB2 AF2 AE2 Y1 Y2 AC1 AB1",
"Y3 W3 W6 V6 W4 W5 W1 V1",
"G2 D1 E1 E2 F2 A2 A3 C2",
"C3 D3 A4 B4 C4 D4 D5 E5",
"F4 G4 K6 K7 K8 L8 J5 J6",
"G6 H6 F7 F8 G8 H8 D6 E6"),
IOStandard("SSTL15")),
Subsignal("dqs_p", Pins("V8 AD5 AD1 V3 C1 B5 J4 H7"),
IOStandard("DIFF_SSTL15")),
Subsignal("dqs_n", Pins("W8 AE5 AE1 V2 B1 A5 H4 G7"),
IOStandard("DIFF_SSTL15")),
Subsignal("clk_p", Pins("M2"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_n", Pins("L2"), IOStandard("DIFF_SSTL15")),
Subsignal("cke", Pins("P4"), IOStandard("SSTL15")),
Subsignal("odt", Pins("R2"), IOStandard("SSTL15")),
Subsignal("reset_n", Pins("N8"), IOStandard("LVCMOS15"))
),
("vadj_on_b", 0, Pins("R16"), IOStandard("LVCMOS25")),
("gtp_refclk", 0,
Subsignal("p", Pins("AA13")),
Subsignal("n", Pins("AB13"))
),
("sfp", 0,
Subsignal("txp", Pins("AC10")),
Subsignal("txn", Pins("AD10")),
Subsignal("rxp", Pins("AC12")),
Subsignal("rxn", Pins("AD12")),
),
("sfp_mgt_clk_sel0", 0, Pins("B26"), IOStandard("LVCMOS25")),
("sfp_mgt_clk_sel1", 0, Pins("C24"), IOStandard("LVCMOS25")),
("sfp_tx_disable_n", 0, Pins("R18"), IOStandard("LVCMOS33")),
("sfp_rx_los", 0, Pins("R23"), IOStandard("LVCMOS33")),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
("HPC", {
"CLK0_M2C_N": "C19",
"CLK0_M2C_P": "D19",
"CLK1_M2C_N": "H22",
"CLK1_M2C_P": "H21",
"LA00_CC_N": "C18",
"LA00_CC_P": "D18",
"LA01_CC_N": "E18",
"LA01_CC_P": "E17",
"LA02_N": "H15",
"LA02_P": "H14",
"LA03_N": "F17",
"LA03_P": "G17",
"LA04_N": "F19",
"LA04_P": "F18",
"LA05_N": "F15",
"LA05_P": "G15",
"LA06_N": "F20",
"LA06_P": "G19",
"LA07_N": "G16",
"LA07_P": "H16",
"LA08_N": "B17",
"LA08_P": "C17",
"LA09_N": "D16",
"LA09_P": "E16",
"LA10_N": "A18",
"LA10_P": "A17",
"LA11_N": "A19",
"LA11_P": "B19",
"LA12_N": "D20",
"LA12_P": "E20",
"LA13_N": "A20",
"LA13_P": "B20",
"LA14_N": "B21",
"LA14_P": "C21",
"LA15_N": "A22",
"LA15_P": "B22",
"LA16_N": "D21",
"LA16_P": "E21",
"LA17_CC_N": "J21",
"LA17_CC_P": "K21",
"LA18_CC_N": "G21",
"LA18_CC_P": "G20",
"LA19_N": "L14",
"LA19_P": "M14",
"LA20_N": "M17",
"LA20_P": "M16",
"LA21_N": "H19",
"LA21_P": "J19",
"LA22_N": "L18",
"LA22_P": "L17",
"LA23_N": "J20",
"LA23_P": "K20",
"LA24_N": "H18",
"LA24_P": "J18",
"LA25_N": "F22",
"LA25_P": "G22",
"LA26_N": "H24",
"LA26_P": "J24",
"LA27_N": "E23",
"LA27_P": "F23",
"LA28_N": "K23",
"LA28_P": "K22",
"LA29_N": "F24",
"LA29_P": "G24",
"LA30_N": "D25",
"LA30_P": "E25",
"LA31_N": "D26",
"LA31_P": "E26",
"LA32_N": "G26",
"LA32_P": "H26",
"LA33_N": "F25",
"LA33_P": "G25",
"PRSNT_M2C_L": "N16",
"PWR_GOOD_FLASH_RST_B": "P15"}
),
("XADC", {
"GPIO0": "H17",
"GPIO1": "E22",
"GPIO2": "K18",
"GPIO3": "L19",
"VAUX0_N": "J16",
"VAUX0_P": "K15",
"VAUX8_N": "J15",
"VAUX8_P": "J14",
}
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk156"
default_clk_period = 6.4
def __init__(self):
XilinxPlatform.__init__(self, "xc7a200t-fbg676-2", _io, _connectors, toolchain="vivado")
self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
def create_programmer(self):
return VivadoProgrammer()
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
try:
self.add_period_constraint(self.lookup_request("clk200").p, 1e9/200e6)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("eth_clocks").rx, 1e9/125e6)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("eth_clocks").tx, 1e9/125e6)
except ConstraintError:
pass

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# This file is Copyright (c) 2015 Yann Sionneau <yann@sionneau.net>
# This file is Copyright (c) 2015 Florent Kermarrec <florent@enjoy-digital.fr>
# This file is Copyright (c) 2018 William D. Jones <thor0505@comcast.net>
# This file is Copyright (c) 2018 Caleb Jamison <cbjamo@gmail.com>
# License: BSD
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
("user_led", 0, Pins("H5"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("J5"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("T9"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("T10"), IOStandard("LVCMOS33")),
("rgb_led", 0,
Subsignal("r", Pins("G6")),
Subsignal("g", Pins("F6")),
Subsignal("b", Pins("E1")),
IOStandard("LVCMOS33"),
),
("rgb_led", 1,
Subsignal("r", Pins("G3")),
Subsignal("g", Pins("J4")),
Subsignal("b", Pins("G4")),
IOStandard("LVCMOS33"),
),
("rgb_led", 2,
Subsignal("r", Pins("J3")),
Subsignal("g", Pins("J2")),
Subsignal("b", Pins("H4")),
IOStandard("LVCMOS33"),
),
("rgb_led", 3,
Subsignal("r", Pins("K1")),
Subsignal("g", Pins("H6")),
Subsignal("b", Pins("K2")),
IOStandard("LVCMOS33"),
),
("user_sw", 0, Pins("A8"), IOStandard("LVCMOS33")),
("user_sw", 1, Pins("C11"), IOStandard("LVCMOS33")),
("user_sw", 2, Pins("C10"), IOStandard("LVCMOS33")),
("user_sw", 3, Pins("A10"), IOStandard("LVCMOS33")),
("user_btn", 0, Pins("D9"), IOStandard("LVCMOS33")),
("user_btn", 1, Pins("C9"), IOStandard("LVCMOS33")),
("user_btn", 2, Pins("B9"), IOStandard("LVCMOS33")),
("user_btn", 3, Pins("B8"), IOStandard("LVCMOS33")),
("clk100", 0, Pins("E3"), IOStandard("LVCMOS33")),
("cpu_reset", 0, Pins("C2"), IOStandard("LVCMOS33")),
("serial", 0,
Subsignal("tx", Pins("D10")),
Subsignal("rx", Pins("A9")),
IOStandard("LVCMOS33")
),
("spi", 0,
Subsignal("clk", Pins("F1")),
Subsignal("cs_n", Pins("C1")),
Subsignal("mosi", Pins("H1")),
Subsignal("miso", Pins("G1")),
IOStandard("LVCMOS33"),
),
("i2c", 0,
Subsignal("scl", Pins("L18")),
Subsignal("sda", Pins("M18")),
Subsignal("scl_pup", Pins("A14")),
Subsignal("sda_pup", Pins("A13")),
IOStandard("LVCMOS33"),
),
("spiflash4x", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("L13")),
Subsignal("dq", Pins("K17", "K18", "L14", "M14")),
IOStandard("LVCMOS33")
),
("spiflash", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("L13")),
Subsignal("mosi", Pins("K17")),
Subsignal("miso", Pins("K18")),
Subsignal("wp", Pins("L14")),
Subsignal("hold", Pins("M14")),
IOStandard("LVCMOS33"),
),
("ddram", 0,
Subsignal("a", Pins(
"R2 M6 N4 T1 N6 R7 V6 U7",
"R8 V7 R6 U6 T6 T8"),
IOStandard("SSTL135")),
Subsignal("ba", Pins("R1 P4 P2"), IOStandard("SSTL135")),
Subsignal("ras_n", Pins("P3"), IOStandard("SSTL135")),
Subsignal("cas_n", Pins("M4"), IOStandard("SSTL135")),
Subsignal("we_n", Pins("P5"), IOStandard("SSTL135")),
Subsignal("cs_n", Pins("U8"), IOStandard("SSTL135")),
Subsignal("dm", Pins("L1 U1"), IOStandard("SSTL135")),
Subsignal("dq", Pins(
"K5 L3 K3 L6 M3 M1 L4 M2",
"V4 T5 U4 V5 V1 T3 U3 R3"),
IOStandard("SSTL135"),
Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("dqs_p", Pins("N2 U2"), IOStandard("DIFF_SSTL135")),
Subsignal("dqs_n", Pins("N1 V2"), IOStandard("DIFF_SSTL135")),
Subsignal("clk_p", Pins("U9"), IOStandard("DIFF_SSTL135")),
Subsignal("clk_n", Pins("V9"), IOStandard("DIFF_SSTL135")),
Subsignal("cke", Pins("N5"), IOStandard("SSTL135")),
Subsignal("odt", Pins("R5"), IOStandard("SSTL135")),
Subsignal("reset_n", Pins("K6"), IOStandard("SSTL135")),
Misc("SLEW=FAST"),
),
("eth_ref_clk", 0, Pins("G18"), IOStandard("LVCMOS33")),
("eth_clocks", 0,
Subsignal("tx", Pins("H16")),
Subsignal("rx", Pins("F15")),
IOStandard("LVCMOS33"),
),
("eth", 0,
Subsignal("rst_n", Pins("C16")),
Subsignal("mdio", Pins("K13")),
Subsignal("mdc", Pins("F16")),
Subsignal("rx_dv", Pins("G16")),
Subsignal("rx_er", Pins("C17")),
Subsignal("rx_data", Pins("D18 E17 E18 G17")),
Subsignal("tx_en", Pins("H15")),
Subsignal("tx_data", Pins("H14 J14 J13 H17")),
Subsignal("col", Pins("D17")),
Subsignal("crs", Pins("G14")),
IOStandard("LVCMOS33"),
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
("pmoda", "G13 B11 A11 D12 D13 B18 A18 K16"),
("pmodb", "E15 E16 D15 C15 J17 J18 K15 J15"),
("pmodc", "U12 V12 V10 V11 U14 V14 T13 U13"),
("pmodd", "D4 D3 F4 F3 E2 D2 H2 G2"),
("ck_io", {
# Outer Digital Header
"ck_io0" : "V15",
"ck_io1" : "U16",
"ck_io2" : "P14",
"ck_io3" : "T11",
"ck_io4" : "R12",
"ck_io5" : "T14",
"ck_io6" : "T15",
"ck_io7" : "T16",
"ck_io8" : "N15",
"ck_io9" : "M16",
"ck_io10" : "V17",
"ck_io11" : "U18",
"ck_io12" : "R17",
"ck_io13" : "P17",
# Inner Digital Header
"ck_io26" : "U11",
"ck_io27" : "V16",
"ck_io28" : "M13",
"ck_io29" : "R10",
"ck_io30" : "R11",
"ck_io31" : "R13",
"ck_io32" : "R15",
"ck_io33" : "P15",
"ck_io34" : "R16",
"ck_io35" : "N16",
"ck_io36" : "N14",
"ck_io37" : "U17",
"ck_io38" : "T18",
"ck_io39" : "R18",
"ck_io40" : "P18",
"ck_io41" : "N17",
# Outer Analog Header as Digital IO
"ck_a0" : "F5",
"ck_a1" : "D8",
"ck_a2" : "C7",
"ck_a3" : "E7",
"ck_a4" : "D7",
"ck_a5" : "D5",
# Inner Analog Header as Digital IO
"ck_io20" : "B7",
"ck_io21" : "B6",
"ck_io22" : "E6",
"ck_io23" : "E5",
"ck_io24" : "A4",
"ck_io25" : "A3",
} ),
("XADC", {
# Outer Analog Header
"vaux4_n" : "C5",
"vaux4_p" : "C6",
"vaux5_n" : "A5",
"vaux5_p" : "A6",
"vaux6_n" : "B4",
"vaux6_p" : "C4",
"vaux7_n" : "A1",
"vaux7_p" : "B1",
"vaux15_n" : "B2",
"vaux15_p" : "B3",
"vaux0_n" : "C14",
"vaux0_p" : "D14",
# Inner Analog Header
"vaux12_n" : "B7",
"vaux12_p" : "B6",
"vaux13_n" : "E6",
"vaux13_p" : "E5",
"vaux14_n" : "A4",
"vaux14_p" : "A3",
# Power Measurements
"vsnsuv_n" : "B17",
"vsnsuv_p" : "B16",
"vsns5v0_n" : "B12",
"vsns5v0_p" : "C12",
"isns5v0_n" : "F14",
"isns5v0_n" : "F13",
"isns0v95_n" : "A16",
"isns0v95_n" : "A15",
} ),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 10.0
def __init__(self, variant="a7-35"):
device = {
"a7-35": "xc7a35ticsg324-1L",
"a7-100": "xc7a100tcsg324-1"
}[variant]
XilinxPlatform.__init__(self, device, _io, _connectors, toolchain="vivado")
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]")
def create_programmer(self):
return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4")

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# This file is Copyright (c) 2018 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
from litex.build.generic_platform import *
from litex.build.microsemi import MicrosemiPlatform
# IOs ----------------------------------------------------------------------------------------------
_io = [
("clk50", 0, Pins("R1"), IOStandard("LVCMOS25")),
("clk50", 1, Pins("J3"), IOStandard("LVCMOS25")),
("rst_n", 0, Pins("F5"), IOStandard("LVCMOS33")),
("user_led", 0, Pins("D6"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("D7"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("D8"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("D9"), IOStandard("LVCMOS33")),
("user_btn", 0, Pins("E13"), IOStandard("LVCMOS33")),
("user_btn", 1, Pins("E14"), IOStandard("LVCMOS33")),
("serial", 0,
Subsignal("tx", Pins("F17")),
Subsignal("rx", Pins("F16")),
IOStandard("LVCMOS33")
),
("spiflash4x", 0,
Subsignal("clk", Pins("J1")),
Subsignal("cs_n", Pins("H1")),
Subsignal("dq", Pins("F2 F1 M7 M8")),
IOStandard("LVCMOS25")
),
("spiflash", 0,
Subsignal("clk", Pins("J1")),
Subsignal("cs_n", Pins("H1")),
Subsignal("mosi", Pins("F2")),
Subsignal("miso", Pins("F1")),
Subsignal("wp", Pins("M7")),
Subsignal("hold", Pins("M8")),
IOStandard("LVCMOS25"),
),
("ddram", 0,
Subsignal("a", Pins(
"U5 U4 V4 W3 V5 W4 Y3 AA3",
"Y4 Y5 AA2 AB2 V6 W6 AB3"),
IOStandard("SSTL15II")),
Subsignal("ba", Pins("V7 Y6 U7"), IOStandard("SSTL15II")),
Subsignal("ras_n", Pins("AA6"), IOStandard("SSTL15II")),
Subsignal("cas_n", Pins("AA5"), IOStandard("SSTL15II")),
Subsignal("we_n", Pins("AB5"), IOStandard("SSTL15II")),
Subsignal("cs_n", Pins("W7"), IOStandard("SSTL15II")),
Subsignal("dm", Pins("Y9 R15"), IOStandard("SSTL15II")),
Subsignal("dq", Pins(
"T7 T8 U8 U9 R10 V9 V10 W9",
"V14 U14 R12 T11 U15 T13 U13 T15"),
IOStandard("SSTL15II")),
Subsignal("dqs_p", Pins("T10 R13"), IOStandard("SSTL15II")),
Subsignal("dqs_n", Pins("U10 T12"), IOStandard("SSTL15II")),
Subsignal("clk_p", Pins("V2"), IOStandard("SSTL15II")),
Subsignal("clk_n", Pins("W2"), IOStandard("SSTL15II")),
Subsignal("cke", Pins("W8"), IOStandard("SSTL15II")),
Subsignal("odt", Pins("AA7"), IOStandard("SSTL15II")),
Subsignal("reset_n", Pins("AB7"), IOStandard("SSTL15II")),
),
("eth_clocks", 0,
Subsignal("tx", Pins("J8")),
Subsignal("rx", Pins("K3")),
IOStandard("LVCMOS25")
),
("eth", 0,
Subsignal("rst_n", Pins("L8"), IOStandard("LVCMOS33")),
Subsignal("int_n", Pins("J4")),
Subsignal("mdio", Pins("H2")),
Subsignal("mdc", Pins("J2")),
Subsignal("rx_ctl", Pins("K5")),
Subsignal("rx_data", Pins("J9 K1 K6 K4")),
Subsignal("tx_ctl", Pins("L5")),
Subsignal("tx_data", Pins("K8 L1 L2 L3")),
IOStandard("LVCMOS25")
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(MicrosemiPlatform):
default_clk_name = "clk50"
default_clk_period = 20.0
def __init__(self):
MicrosemiPlatform.__init__(self, "MPF300TS_ES-FCG484-1", _io)

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# This file is Copyright (c) 2013 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster
# IOs ----------------------------------------------------------------------------------------------
_io = [
("clk50", 0, Pins("R8"), IOStandard("3.3-V LVTTL")),
("user_led", 0, Pins("A15"), IOStandard("3.3-V LVTTL")),
("user_led", 1, Pins("A13"), IOStandard("3.3-V LVTTL")),
("user_led", 2, Pins("B13"), IOStandard("3.3-V LVTTL")),
("user_led", 3, Pins("A11"), IOStandard("3.3-V LVTTL")),
("user_led", 4, Pins("D1"), IOStandard("3.3-V LVTTL")),
("user_led", 5, Pins("F3"), IOStandard("3.3-V LVTTL")),
("user_led", 6, Pins("B1"), IOStandard("3.3-V LVTTL")),
("user_led", 7, Pins("L3"), IOStandard("3.3-V LVTTL")),
("key", 0, Pins("J15"), IOStandard("3.3-V LVTTL")),
("key", 1, Pins("E1"), IOStandard("3.3-V LVTTL")),
("sw", 0, Pins("M1"), IOStandard("3.3-V LVTTL")),
("sw", 1, Pins("T8"), IOStandard("3.3-V LVTTL")),
("sw", 2, Pins("B9"), IOStandard("3.3-V LVTTL")),
("sw", 3, Pins("M15"), IOStandard("3.3-V LVTTL")),
("serial", 0,
Subsignal("tx", Pins("B4"), IOStandard("3.3-V LVTTL")),
Subsignal("rx", Pins("B5"), IOStandard("3.3-V LVTTL"))
),
("sdram_clock", 0, Pins("R4"), IOStandard("3.3-V LVTTL")),
("sdram", 0,
Subsignal("a", Pins("P2 N5 N6 M8 P8 T7 N8 T6 R1 P1 N2 N1 L4")),
Subsignal("ba", Pins("M7 M6")),
Subsignal("cs_n", Pins("P6")),
Subsignal("cke", Pins("L7")),
Subsignal("ras_n", Pins("L2")),
Subsignal("cas_n", Pins("L1")),
Subsignal("we_n", Pins("C2")),
Subsignal("dq", Pins("G2 G1 L8 K5 K2 J2 J1 R7 T4 T2 T3 R3 R5 P3 N3 K1")),
Subsignal("dm", Pins("R6 T5")),
IOStandard("3.3-V LVTTL")
),
("epcs", 0,
Subsignal("data0", Pins("H2")),
Subsignal("dclk", Pins("H1")),
Subsignal("ncs0", Pins("D2")),
Subsignal("asd0", Pins("C1")),
IOStandard("3.3-V LVTTL")
),
("i2c", 0,
Subsignal("sclk", Pins("F2")),
Subsignal("sdat", Pins("F1")),
IOStandard("3.3-V LVTTL")
),
("g_sensor", 0,
Subsignal("cs_n", Pins("G5")),
Subsignal("int", Pins("M2")),
IOStandard("3.3-V LVTTL")
),
("adc", 0,
Subsignal("cs_n", Pins("A10")),
Subsignal("saddr", Pins("B10")),
Subsignal("sclk", Pins("B14")),
Subsignal("sdat", Pins("A9")),
IOStandard("3.3-V LVTTL")
),
("gpio_0", 0,
Pins("D3 C3 A2 A3 B3 B4 A4 B5 A5 D5 B6 A6 B7 D6 A7 C6",
"C8 E6 E7 D8 E8 F8 F9 E9 C9 D9 E11 E10 C11 B11 A12 D11",
"D12 B12"),
IOStandard("3.3-V LVTTL")
),
("gpio_1", 0,
Pins("F13 T15 T14 T13 R13 T12 R12 T11 T10 R11 P11 R10 N12 P9 N9 N11",
"L16 K16 R16 L15 P15 P16 R14 N16 N15 P14 L14 N14 M10 L13 J16 K15",
"J13 J14"),
IOStandard("3.3-V LVTTL")
),
("gpio_2", 0,
Pins("A14 B16 C14 C16 C15 D16 D15 D14 F15 F16 F14 G16 G15"),
IOStandard("3.3-V LVTTL")
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(AlteraPlatform):
default_clk_name = "clk50"
default_clk_period = 20
def __init__(self):
AlteraPlatform.__init__(self, "EP4CE22F17C6", _io)
def create_programmer(self):
return USBBlaster()

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from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster
_io = [
("clk10", 0, Pins("N5"), IOStandard("3.3-V LVTTL")),
("clk50", 0, Pins("P11"), IOStandard("3.3-V LVTTL")),
("clk50", 1, Pins("N14"), IOStandard("3.3-V LVTTL")),
("serial", 0,
Subsignal("tx", Pins("V10"), IOStandard("3.3-V LVTTL")), # JP1 GPIO[0]
Subsignal("rx", Pins("W10"), IOStandard("3.3-V LVTTL")) # JP1 GPIO[1]
),
("user_led", 0, Pins("A8"), IOStandard("3.3-V LVTTL")),
("user_led", 1, Pins("A9"), IOStandard("3.3-V LVTTL")),
("user_led", 2, Pins("A10"), IOStandard("3.3-V LVTTL")),
("user_led", 3, Pins("B10"), IOStandard("3.3-V LVTTL")),
("user_led", 4, Pins("D13"), IOStandard("3.3-V LVTTL")),
("user_led", 5, Pins("C13"), IOStandard("3.3-V LVTTL")),
("user_led", 6, Pins("E14"), IOStandard("3.3-V LVTTL")),
("user_led", 7, Pins("D14"), IOStandard("3.3-V LVTTL")),
("user_led", 8, Pins("A11"), IOStandard("3.3-V LVTTL")),
("user_led", 9, Pins("B11"), IOStandard("3.3-V LVTTL")),
("user_btn", 0, Pins("B8"), IOStandard("3.3-V LVTTL")),
("user_btn", 1, Pins("A7"), IOStandard("3.3-V LVTTL")),
("user_sw", 0, Pins("C10"), IOStandard("3.3-V LVTTL")),
("user_sw", 1, Pins("C11"), IOStandard("3.3-V LVTTL")),
("user_sw", 2, Pins("D12"), IOStandard("3.3-V LVTTL")),
("user_sw", 3, Pins("C12"), IOStandard("3.3-V LVTTL")),
("user_sw", 4, Pins("A12"), IOStandard("3.3-V LVTTL")),
("user_sw", 5, Pins("B12"), IOStandard("3.3-V LVTTL")),
("user_sw", 6, Pins("A13"), IOStandard("3.3-V LVTTL")),
("user_sw", 7, Pins("A14"), IOStandard("3.3-V LVTTL")),
("user_sw", 8, Pins("B14"), IOStandard("3.3-V LVTTL")),
("user_sw", 9, Pins("F15"), IOStandard("3.3-V LVTTL")),
# 7-segment displays
("seven_seg", 0, Pins("C14 E15 C15 C16 E16 D17 C17 D15"), IOStandard("3.3-V LVTTL")),
("seven_seg", 1, Pins("C18 D18 E18 B16 A17 A18 B17 A16"), IOStandard("3.3-V LVTTL")),
("seven_seg", 2, Pins("B20 A20 B19 A21 B21 C22 B22 A19"), IOStandard("3.3-V LVTTL")),
("seven_seg", 3, Pins("F21 E22 E21 C19 C20 D19 E17 D22"), IOStandard("3.3-V LVTTL")),
("seven_seg", 4, Pins("F18 E20 E19 J18 H19 F19 F20 F17"), IOStandard("3.3-V LVTTL")),
("seven_seg", 5, Pins("J20 K20 L18 N18 M20 N19 N20 L19"), IOStandard("3.3-V LVTTL")),
("gpio_0", 0,
Pins("V10 W10 V9 W9 V8 W8 V7 W7 W6 V5 W5 AA15 AA14 W13 W12 AB13 AB12 Y11 AB11 W11 AB10 AA10 AA9 Y8 AA8 Y7 AA7 Y6 AA6 Y5 AA5 Y4 AB3 Y3 AB2 AA2"),
IOStandard("3.3-V LVTTL")
),
("gpio_1", 0,
Pins("AB5 AB6 AB7 AB8 AB9 Y10 AA11 AA12 AB17 AA17 AB19 AA19 Y19 AB20 AB21 AA20 F16"),
IOStandard("3.3-V LVTTL")
),
("vga_out", 0,
Subsignal("hsync_n", Pins("N3")),
Subsignal("vsync_n", Pins("N1")),
Subsignal("r", Pins("AA1 V1 Y2 Y1")),
Subsignal("g", Pins("W1 T2 R2 R1")),
Subsignal("b", Pins("P1 T1 P4 N2")),
IOStandard("3.3-V LVTTL")
),
("sdram_clock", 0, Pins("L14"), IOStandard("3.3-V LVTTL")),
("sdram", 0,
Subsignal("a", Pins("U17 W19 V18 U18 U19 T18 T19 R18 P18 P19 T20 P20 R20")),
Subsignal("ba", Pins("T21 T22")),
Subsignal("cs_n", Pins("U20")),
Subsignal("cke", Pins("N22")),
Subsignal("ras_n", Pins("U22")),
Subsignal("cas_n", Pins("U21")),
Subsignal("we_n", Pins("V20")),
Subsignal("dq", Pins("Y21 Y20 AA22 AA21 Y22 W22 W20 V21 P21 J22 H21 H22 G22 G20 G19 F22")),
Subsignal("dm", Pins("V22 J21")),
IOStandard("3.3-V LVTTL")
),
("accelerometer", 0,
Subsignal("int1", Pins("Y14")),
Subsignal("int1", Pins("Y13")),
Subsignal("mosi", Pins("V11")),
Subsignal("miso", Pins("V12")),
Subsignal("clk", Pins("AB15")),
Subsignal("cs_n", Pins("AB16")),
IOStandard("3.3-V LVTTL")
)
]
class Platform(AlteraPlatform):
default_clk_name = "clk50"
default_clk_period = 20
create_rbf = False
def __init__(self):
AlteraPlatform.__init__(self, "10M50DAF484C7G", _io)
def create_programmer(self):
return USBBlaster()

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# SPDX-License-Identifier: BSD-2-Clause
#
# Copyright (c) 2019 Antony Pavlov <antonynpavlov@gmail.com>
from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
# IOs ------------------------------------------------------------------
_io = [
("clk50", 0, Pins("AF14"), IOStandard("3.3-V LVTTL")),
("serial", 0,
Subsignal("tx", Pins("AC18"), IOStandard("3.3-V LVTTL")), # JP1 GPIO[0]
Subsignal("rx", Pins("Y17"), IOStandard("3.3-V LVTTL")) # JP1 GPIO[1]
),
("sdram_clock", 0, Pins("AH12"), IOStandard("3.3-V LVTTL")),
("sdram", 0,
Subsignal("a", Pins("AK14 AH14 AG15 AE14 AB15 AC14 AD14 AF15 AH15 AG13 AG12 AH13 AJ14")),
Subsignal("ba", Pins("AF13 AJ12")),
Subsignal("cs_n", Pins("AG11")),
Subsignal("cke", Pins("AK13")),
Subsignal("ras_n", Pins("AE13")),
Subsignal("cas_n", Pins("AF11")),
Subsignal("we_n", Pins("AA13")),
Subsignal("dq", Pins("AK6 AJ7 AK7 AK8 AK9 AG10 AK11 AJ11 AH10 AJ10 AJ9 AH9 AH8 AH7 AJ6 AJ5")),
Subsignal("dm", Pins("AB13 AK12")),
IOStandard("3.3-V LVTTL")
),
]
# Platform -------------------------------------------------------------
class Platform(AlteraPlatform):
default_clk_name = "clk50"
default_clk_period = 20
def __init__(self):
AlteraPlatform.__init__(self, "5CSEMA5F31C6", _io)

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# SPDX-License-Identifier: BSD-2-Clause
#
# Copyright (c) 2019 Antony Pavlov <antonynpavlov@gmail.com>
from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
# IOs ------------------------------------------------------------------
_io = [
("clk50", 0, Pins("Y2"), IOStandard("3.3-V LVTTL")),
("serial", 0,
Subsignal("tx", Pins("AB22"), IOStandard("3.3-V LVTTL")), # JP5 GPIO[0]
Subsignal("rx", Pins("AC15"), IOStandard("3.3-V LVTTL")) # JP5 GPIO[1]
),
("sdram_clock", 0, Pins("AE5"), IOStandard("3.3-V LVTTL")),
("sdram", 0,
Subsignal("a", Pins("R6 V8 U8 P1 V5 W8 W7 AA7 Y5 Y6 R5 AA5 Y7")),
Subsignal("ba", Pins("U7 R4")),
Subsignal("cs_n", Pins("T4")),
Subsignal("cke", Pins("AA6")),
Subsignal("ras_n", Pins("U6")),
Subsignal("cas_n", Pins("V7")),
Subsignal("we_n", Pins("V6")),
Subsignal("dq", Pins("W3 W2 V4 W1 V3 V2 V1 U3 Y3 Y4 AB1 AA3 AB2 AC1 AB3 AC2")),
Subsignal("dm", Pins("U2 W4")),
IOStandard("3.3-V LVTTL")
),
]
# Platform -------------------------------------------------------------
class Platform(AlteraPlatform):
default_clk_name = "clk50"
default_clk_period = 20
def __init__(self):
AlteraPlatform.__init__(self, "EP4CE115F29C7", _io)

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from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
("user_led", 0, Pins("T28"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("V19"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("U30"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("U29"), IOStandard("LVCMOS33")),
("user_led", 4, Pins("V20"), IOStandard("LVCMOS33")),
("user_led", 5, Pins("V26"), IOStandard("LVCMOS33")),
("user_led", 6, Pins("W24"), IOStandard("LVCMOS33")),
("user_led", 7, Pins("W23"), IOStandard("LVCMOS33")),
("cpu_reset_n", 0, Pins("R19"), IOStandard("LVCMOS33")),
("user_btn_c", 0, Pins("E18"), IOStandard("LVCMOS33")),
("user_btn_d", 0, Pins("M19"), IOStandard("LVCMOS33")),
("user_btn_l", 0, Pins("M20"), IOStandard("LVCMOS33")),
("user_btn_r", 0, Pins("C19"), IOStandard("LVCMOS33")),
("user_btn_u", 0, Pins("B19"), IOStandard("LVCMOS33")),
("user_sw", 0, Pins("G19"), IOStandard("LVCMOS12")),
("user_sw", 1, Pins("G25"), IOStandard("LVCMOS12")),
("user_sw", 2, Pins("H24"), IOStandard("LVCMOS12")),
("user_sw", 3, Pins("K19"), IOStandard("LVCMOS12")),
("user_sw", 4, Pins("N19"), IOStandard("LVCMOS12")),
("user_sw", 5, Pins("P19"), IOStandard("LVCMOS12")),
("user_sw", 6, Pins("P26"), IOStandard("LVCMOS33")),
("user_sw", 7, Pins("P27"), IOStandard("LVCMOS33")),
("clk200", 0,
Subsignal("p", Pins("AD12"), IOStandard("LVDS")),
Subsignal("n", Pins("AD11"), IOStandard("LVDS"))
),
("serial", 0,
Subsignal("tx", Pins("Y23")),
Subsignal("rx", Pins("Y20")),
IOStandard("LVCMOS33")
),
("ddram", 0,
Subsignal("a", Pins(
"AC12 AE8 AD8 AC10 AD9 AA13 AA10 AA11",
"Y10 Y11 AB8 AA8 AB12 AA12 AH9"),
IOStandard("SSTL15")),
Subsignal("ba", Pins("AE9 AB10 AC11"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("AE11"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("AF11"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("AG13"), IOStandard("SSTL15")),
Subsignal("cs_n", Pins("AH12"), IOStandard("SSTL15")),
Subsignal("dm", Pins("AD4 AF3 AH4 AF8"),
IOStandard("SSTL15")),
Subsignal("dq", Pins(
"AD3 AC2 AC1 AC5 AC4 AD6 AE6 AC7",
"AF2 AE1 AF1 AE4 AE3 AE5 AF5 AF6",
"AJ4 AH6 AH5 AH2 AJ2 AJ1 AK1 AJ3",
"AF7 AG7 AJ6 AK6 AJ8 AK8 AK5 AK4"),
IOStandard("SSTL15_T_DCI")),
Subsignal("dqs_p", Pins("AD2 AG4 AG2 AH7"),
IOStandard("DIFF_SSTL15")),
Subsignal("dqs_n", Pins("AD1 AG3 AH1 AJ7"),
IOStandard("DIFF_SSTL15")),
Subsignal("clk_p", Pins("AB9"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_n", Pins("AC9"), IOStandard("DIFF_SSTL15")),
Subsignal("cke", Pins("AJ9"), IOStandard("SSTL15")),
Subsignal("odt", Pins("AK9"), IOStandard("SSTL15")),
Subsignal("reset_n", Pins("AG5"), IOStandard("LVCMOS15")),
Misc("SLEW=FAST"),
Misc("VCCAUX_IO=HIGH")
),
("eth_clocks", 0,
Subsignal("tx", Pins("AE10")),
Subsignal("rx", Pins("AG10")),
IOStandard("LVCMOS15")
),
("eth", 0,
Subsignal("rst_n", Pins("AH24"), IOStandard("LVCMOS33")),
Subsignal("int_n", Pins("AK16"), IOStandard("LVCMOS18")),
Subsignal("mdio", Pins("AG12"), IOStandard("LVCMOS15")),
Subsignal("mdc", Pins("AF12"), IOStandard("LVCMOS15")),
Subsignal("rx_ctl", Pins("AH11"), IOStandard("LVCMOS15")),
Subsignal("rx_data", Pins("AJ14 AH14 AK13 AJ13"), IOStandard("LVCMOS15")),
Subsignal("tx_ctl", Pins(" AK14"), IOStandard("LVCMOS15")),
Subsignal("tx_data", Pins("AJ12 AK11 AJ11 AK10"), IOStandard("LVCMOS15")),
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
("HPC", {
"DP0_C2M_P": "Y2",
"DP0_C2M_N": "Y1",
"DP0_M2C_P": "AA4",
"DP0_M2C_N": "AA3",
"GBTCLK0_M2C_P": "L8",
"GBTCLK0_M2C_N": "L7",
}
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk200"
default_clk_period = 5
def __init__(self):
XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado")
def create_programmer(self):
return VivadoProgrammer()
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
try:
self.add_period_constraint(self.lookup_request("eth_clocks").rx, 1e9/125e6)
except ConstraintError:
pass

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from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
("user_led", 0, Pins("AB8"), IOStandard("LVCMOS15")),
("user_led", 1, Pins("AA8"), IOStandard("LVCMOS15")),
("user_led", 2, Pins("AC9"), IOStandard("LVCMOS15")),
("user_led", 3, Pins("AB9"), IOStandard("LVCMOS15")),
("user_led", 4, Pins("AE26"), IOStandard("LVCMOS25")),
("user_led", 5, Pins("G19"), IOStandard("LVCMOS25")),
("user_led", 6, Pins("E18"), IOStandard("LVCMOS25")),
("user_led", 7, Pins("F16"), IOStandard("LVCMOS25")),
("cpu_reset", 0, Pins("AB7"), IOStandard("LVCMOS15")),
("user_btn_c", 0, Pins("G12"), IOStandard("LVCMOS25")),
("user_btn_n", 0, Pins("AA12"), IOStandard("LVCMOS15")),
("user_btn_s", 0, Pins("AB12"), IOStandard("LVCMOS15")),
("user_btn_w", 0, Pins("AC6"), IOStandard("LVCMOS15")),
("user_btn_e", 0, Pins("AG5"), IOStandard("LVCMOS15")),
("user_dip_btn", 0, Pins("Y29"), IOStandard("LVCMOS25")),
("user_dip_btn", 1, Pins("W29"), IOStandard("LVCMOS25")),
("user_dip_btn", 2, Pins("AA28"), IOStandard("LVCMOS25")),
("user_dip_btn", 3, Pins("Y28"), IOStandard("LVCMOS25")),
("user_sma_clock", 0,
Subsignal("p", Pins("L25"), IOStandard("LVDS_25"),
Misc("DIFF_TERM=TRUE")),
Subsignal("n", Pins("K25"), IOStandard("LVDS_25"),
Misc("DIFF_TERM=TRUE"))
),
("user_sma_clock_p", 0, Pins("L25"), IOStandard("LVCMOS25")),
("user_sma_clock_n", 0, Pins("K25"), IOStandard("LVCMOS25")),
("user_sma_gpio_p", 0, Pins("Y23"), IOStandard("LVCMOS25")),
("user_sma_gpio_n", 0, Pins("Y24"), IOStandard("LVCMOS25")),
("clk200", 0,
Subsignal("p", Pins("AD12"), IOStandard("LVDS")),
Subsignal("n", Pins("AD11"), IOStandard("LVDS"))
),
("clk156", 0,
Subsignal("p", Pins("K28"), IOStandard("LVDS_25")),
Subsignal("n", Pins("K29"), IOStandard("LVDS_25"))
),
("i2c", 0,
Subsignal("scl", Pins("K21")),
Subsignal("sda", Pins("L21")),
IOStandard("LVCMOS25")),
("serial", 0,
Subsignal("cts", Pins("L27")),
Subsignal("rts", Pins("K23")),
Subsignal("tx", Pins("K24")),
Subsignal("rx", Pins("M19")),
IOStandard("LVCMOS25")
),
("spiflash", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("U19")),
Subsignal("dq", Pins("P24", "R25", "R20", "R21")),
IOStandard("LVCMOS25")
),
("mmc", 0,
Subsignal("wp", Pins("Y21")),
Subsignal("det", Pins("AA21")),
Subsignal("cmd", Pins("AB22")),
Subsignal("clk", Pins("AB23")),
Subsignal("dat", Pins("AC20 AA23 AA22 AC21")),
IOStandard("LVCMOS25")),
("mmc_spi", 0,
Subsignal("miso", Pins("AC20"), Misc("PULLUP")),
Subsignal("clk", Pins("AB23")),
Subsignal("mosi", Pins("AB22")),
Subsignal("cs_n", Pins("AC21")),
IOStandard("LVCMOS25")),
("lcd", 0,
Subsignal("db", Pins("AA13 AA10 AA11 Y10")),
Subsignal("e", Pins("AB10")),
Subsignal("rs", Pins("Y11")),
Subsignal("rw", Pins("AB13")),
IOStandard("LVCMOS15")),
("rotary", 0,
Subsignal("a", Pins("Y26")),
Subsignal("b", Pins("Y25")),
Subsignal("push", Pins("AA26")),
IOStandard("LVCMOS25")),
("hdmi", 0,
Subsignal("d", Pins("B23 A23 E23 D23 F25 E25 E24 D24 F26 E26 G23 G24 J19 H19 L17 L18 K19 K20")),
Subsignal("de", Pins("H17")),
Subsignal("clk", Pins("K18")),
Subsignal("vsync", Pins("H20")),
Subsignal("hsync", Pins("J18")),
Subsignal("int", Pins("AH24")),
Subsignal("spdif", Pins("J17")),
Subsignal("spdif_out", Pins("G20")),
IOStandard("LVCMOS25")),
("ddram", 0,
Subsignal("a", Pins(
"AH12 AG13 AG12 AF12 AJ12 AJ13 AJ14 AH14",
"AK13 AK14 AF13 AE13 AJ11 AH11 AK10 AK11"),
IOStandard("SSTL15")),
Subsignal("ba", Pins("AH9 AG9 AK9"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("AD9"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("AC11"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("AE9"), IOStandard("SSTL15")),
Subsignal("cs_n", Pins("AC12"), IOStandard("SSTL15")),
Subsignal("dm", Pins("Y16 AB17 AF17 AE16 AK5 AJ3 AF6 AC7"),
IOStandard("SSTL15")),
Subsignal("dq", Pins(
"AA15 AA16 AC14 AD14 AA17 AB15 AE15 Y15",
"AB19 AD16 AC19 AD17 AA18 AB18 AE18 AD18",
"AG19 AK19 AG18 AF18 AH19 AJ19 AE19 AD19",
"AK16 AJ17 AG15 AF15 AH17 AG14 AH15 AK15",
"AK8 AK6 AG7 AF7 AF8 AK4 AJ8 AJ6",
"AH5 AH6 AJ2 AH2 AH4 AJ4 AK1 AJ1",
"AF1 AF2 AE4 AE3 AF3 AF5 AE1 AE5",
"AC1 AD3 AC4 AC5 AE6 AD6 AC2 AD4"),
IOStandard("SSTL15_T_DCI")),
Subsignal("dqs_p", Pins("AC16 Y19 AJ18 AH16 AH7 AG2 AG4 AD2"),
IOStandard("DIFF_SSTL15")),
Subsignal("dqs_n", Pins("AC15 Y18 AK18 AJ16 AJ7 AH1 AG3 AD1"),
IOStandard("DIFF_SSTL15")),
Subsignal("clk_p", Pins("AG10"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_n", Pins("AH10"), IOStandard("DIFF_SSTL15")),
Subsignal("cke", Pins("AF10"), IOStandard("SSTL15")),
Subsignal("odt", Pins("AD8"), IOStandard("SSTL15")),
Subsignal("reset_n", Pins("AK3"), IOStandard("LVCMOS15")),
Misc("SLEW=FAST"),
Misc("VCCAUX_IO=HIGH")
),
("ddram_dual_rank", 0,
Subsignal("a", Pins(
"AH12 AG13 AG12 AF12 AJ12 AJ13 AJ14 AH14",
"AK13 AK14 AF13 AE13 AJ11 AH11 AK10 AK11"),
IOStandard("SSTL15")),
Subsignal("ba", Pins("AH9 AG9 AK9"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("AD9"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("AC11"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("AE9"), IOStandard("SSTL15")),
Subsignal("cs_n", Pins("AC12 AE8"), IOStandard("SSTL15")),
Subsignal("dm", Pins("Y16 AB17 AF17 AE16 AK5 AJ3 AF6 AC7"),
IOStandard("SSTL15")),
Subsignal("dq", Pins(
"AA15 AA16 AC14 AD14 AA17 AB15 AE15 Y15",
"AB19 AD16 AC19 AD17 AA18 AB18 AE18 AD18",
"AG19 AK19 AG18 AF18 AH19 AJ19 AE19 AD19",
"AK16 AJ17 AG15 AF15 AH17 AG14 AH15 AK15",
"AK8 AK6 AG7 AF7 AF8 AK4 AJ8 AJ6",
"AH5 AH6 AJ2 AH2 AH4 AJ4 AK1 AJ1",
"AF1 AF2 AE4 AE3 AF3 AF5 AE1 AE5",
"AC1 AD3 AC4 AC5 AE6 AD6 AC2 AD4"),
IOStandard("SSTL15_T_DCI")),
Subsignal("dqs_p", Pins("AC16 Y19 AJ18 AH16 AH7 AG2 AG4 AD2"),
IOStandard("DIFF_SSTL15")),
Subsignal("dqs_n", Pins("AC15 Y18 AK18 AJ16 AJ7 AH1 AG3 AD1"),
IOStandard("DIFF_SSTL15")),
Subsignal("clk_p", Pins("AG10 AE11"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_n", Pins("AH10 AF11"), IOStandard("DIFF_SSTL15")),
Subsignal("cke", Pins("AF10 AE10"), IOStandard("SSTL15")),
Subsignal("odt", Pins("AD8 AC10"), IOStandard("SSTL15")),
Subsignal("reset_n", Pins("AK3"), IOStandard("LVCMOS15")),
Misc("SLEW=FAST"),
Misc("VCCAUX_IO=HIGH")
),
("eth_clocks", 0,
Subsignal("tx", Pins("M28")),
Subsignal("gtx", Pins("K30")),
Subsignal("rx", Pins("U27")),
IOStandard("LVCMOS25")
),
("eth", 0,
Subsignal("rst_n", Pins("L20")),
Subsignal("int_n", Pins("N30")),
Subsignal("mdio", Pins("J21")),
Subsignal("mdc", Pins("R23")),
Subsignal("rx_dv", Pins("R28")),
Subsignal("rx_er", Pins("V26")),
Subsignal("rx_data", Pins("U30 U25 T25 U28 R19 T27 T26 T28")),
Subsignal("tx_en", Pins("M27")),
Subsignal("tx_er", Pins("N29")),
Subsignal("tx_data", Pins("N27 N25 M29 L28 J26 K26 L30 J28")),
Subsignal("col", Pins("W19")),
Subsignal("crs", Pins("R30")),
IOStandard("LVCMOS25")
),
("pcie_x1", 0,
Subsignal("rst_n", Pins("G25"), IOStandard("LVCMOS25")),
Subsignal("clk_p", Pins("U8")),
Subsignal("clk_n", Pins("U7")),
Subsignal("rx_p", Pins("M6")),
Subsignal("rx_n", Pins("M5")),
Subsignal("tx_p", Pins("L4")),
Subsignal("tx_n", Pins("L3"))
),
("pcie_x2", 0,
Subsignal("rst_n", Pins("G25"), IOStandard("LVCMOS25")),
Subsignal("clk_p", Pins("U8")),
Subsignal("clk_n", Pins("U7")),
Subsignal("rx_p", Pins("M6 P6")),
Subsignal("rx_n", Pins("M5 P5")),
Subsignal("tx_p", Pins("L4 M2")),
Subsignal("tx_n", Pins("L3 M1"))
),
("pcie_x4", 0,
Subsignal("rst_n", Pins("G25"), IOStandard("LVCMOS25")),
Subsignal("clk_p", Pins("U8")),
Subsignal("clk_n", Pins("U7")),
Subsignal("rx_p", Pins("M6 P6 R4 T6")),
Subsignal("rx_n", Pins("M5 P5 R3 T5")),
Subsignal("tx_p", Pins("L4 M2 N4 P2")),
Subsignal("tx_n", Pins("L3 M1 N3 P1"))
),
("pcie_x8", 0,
Subsignal("rst_n", Pins("G25"), IOStandard("LVCMOS25")),
Subsignal("clk_p", Pins("U8")),
Subsignal("clk_n", Pins("U7")),
Subsignal("rx_p", Pins("M6 P6 R4 T6 V6 W4 Y6 AA4")),
Subsignal("rx_n", Pins("M5 P5 R3 T5 V5 W3 Y5 AA3")),
Subsignal("tx_p", Pins("L4 M2 N4 P2 T2 U4 V2 Y2")),
Subsignal("tx_n", Pins("L3 M1 N3 P1 T1 U3 V1 Y1"))
),
("vadj_on_b", 0, Pins("J27"), IOStandard("LVCMOS25")),
("sgmii_clock", 0,
Subsignal("p", Pins("G8")),
Subsignal("n", Pins("G7"))
),
("user_sma_mgt_refclk", 0,
Subsignal("p", Pins("J8")),
Subsignal("n", Pins("J7"))
),
("user_sma_mgt_tx", 0,
Subsignal("p", Pins("K2")),
Subsignal("n", Pins("K1"))
),
("user_sma_mgt_rx", 0,
Subsignal("p", Pins("K6")),
Subsignal("n", Pins("K5"))
),
("sfp", 0, # inverted prior to HW rev 1.1
Subsignal("txp", Pins("H2")),
Subsignal("txn", Pins("H1")),
Subsignal("rxp", Pins("G4")),
Subsignal("rxn", Pins("G3")),
),
("sfp_tx", 0, # inverted prior to HW rev 1.1
Subsignal("p", Pins("H2")),
Subsignal("n", Pins("H1"))
),
("sfp_rx", 0, # inverted prior to HW rev 1.1
Subsignal("p", Pins("G4")),
Subsignal("n", Pins("G3"))
),
("sfp_tx_disable_n", 0, Pins("Y20"), IOStandard("LVCMOS25")),
("sfp_rx_los", 0, Pins("P19"), IOStandard("LVCMOS25")),
("si5324", 0,
Subsignal("rst_n", Pins("AE20"), IOStandard("LVCMOS25")),
Subsignal("int", Pins("AG24"), IOStandard("LVCMOS25"))
),
("si5324_clkin", 0,
Subsignal("p", Pins("W27"), IOStandard("LVDS_25")),
Subsignal("n", Pins("W28"), IOStandard("LVDS_25"))
),
("si5324_clkout", 0,
Subsignal("p", Pins("L8")),
Subsignal("n", Pins("L7"))
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
("HPC", {
"DP1_M2C_P": "D6",
"DP1_M2C_N": "D5",
"DP2_M2C_P": "B6",
"DP2_M2C_N": "B5",
"DP3_M2C_P": "A8",
"DP3_M2C_N": "A7",
"DP1_C2M_P": "C4",
"DP1_C2M_N": "C3",
"DP2_C2M_P": "B2",
"DP2_C2M_N": "B1",
"DP3_C2M_P": "A4",
"DP3_C2M_N": "A3",
"DP0_C2M_P": "D2",
"DP0_C2M_N": "D1",
"DP0_M2C_P": "E4",
"DP0_M2C_N": "E3",
"LA06_P" : "H30",
"LA06_N" : "G30",
"LA10_P" : "D29",
"LA10_N" : "C30",
"LA14_P": "B28",
"LA14_N": "A28",
"LA18_CC_P": "F21",
"LA18_CC_N": "E21",
"LA27_P": "C19",
"LA27_N": "B19",
"HA01_CC_P": "H14",
"HA01_CC_N": "G14",
"HA05_P": "F15",
"HA05_N": "E16",
"HA09_P": "F12",
"HA09_N": "E13",
"HA13_P": "L16",
"HA13_N": "K16",
"HA16_P": "L15",
"HA16_N": "K15",
"HA20_P": "K13",
"HA20_N": "J13",
"CLK1_M2C_P": "D17",
"CLK1_M2C_N": "D18",
"LA00_CC_P": "C25",
"LA00_CC_N": "B25",
"LA03_P": "H26",
"LA03_N": "H27",
"LA08_P": "E29",
"LA08_N": "E30",
"LA12_P": "C29",
"LA12_N": "B29",
"LA16_P": "B27",
"LA16_N": "A27",
"LA20_P": "E19",
"LA20_N": "D19",
"LA22_P": "C20",
"LA22_N": "B20",
"LA25_P": "G17",
"LA25_N": "F17",
"LA29_P": "C17",
"LA29_N": "B17",
"LA31_P": "G22",
"LA31_N": "F22",
"LA33_P": "H21",
"LA33_N": "H22",
"HA03_P": "C12",
"HA03_N": "B12",
"HA07_P": "B14",
"HA07_N": "A15",
"HA11_P": "B13",
"HA11_N": "A13",
"HA14_P": "J16",
"HA14_N": "H16",
"HA18_P": "K14",
"HA18_N": "J14",
"HA22_P": "L11",
"HA22_N": "K11",
"GBTCLK1_M2C_P": "E8",
"GBTCLK1_M2C_N": "E7",
"GBTCLK0_M2C_P": "C8",
"GBTCLK0_M2C_N": "C7",
"LA01_CC_P": "D26",
"LA01_CC_N": "C26",
"LA05_P": "G29",
"LA05_N": "F30",
"LA09_P": "B30",
"LA09_N": "A30",
"LA13_P": "A25",
"LA13_N": "A26",
"LA17_CC_P": "F20",
"LA17_CC_N": "E20",
"LA23_P": "B22",
"LA23_N": "A22",
"LA26_P": "B18",
"LA26_N": "A18",
"PG_M2C": "J29",
"HA00_CC_P": "D12",
"HA00_CC_N": "D13",
"HA04_P": "F11",
"HA04_N": "E11",
"HA08_P": "E14",
"HA08_N": "E15",
"HA12_P": "C15",
"HA12_N": "B15",
"HA15_P": "H15",
"HA15_N": "G15",
"HA19_P": "H11",
"HA19_N": "H12",
"PRSNT_M2C_B": "M20",
"CLK0_M2C_P": "D27",
"CLK0_M2C_N": "C27",
"LA02_P": "H24",
"LA02_N": "H25",
"LA04_P": "G28",
"LA04_N": "F28",
"LA07_P": "E28",
"LA07_N": "D28",
"LA11_P": "G27",
"LA11_N": "F27",
"LA15_P": "C24",
"LA15_N": "B24",
"LA19_P": "G18",
"LA19_N": "F18",
"LA21_P": "A20",
"LA21_N": "A21",
"LA24_P": "A16",
"LA24_N": "A17",
"LA28_P": "D16",
"LA28_N": "C16",
"LA30_P": "D22",
"LA30_N": "C22",
"LA32_P": "D21",
"LA32_N": "C21",
"HA02_P": "D11",
"HA02_N": "C11",
"HA06_P": "D14",
"HA06_N": "C14",
"HA10_P": "A11",
"HA10_N": "A12",
"HA17_CC_P": "G13",
"HA17_CC_N": "F13",
"HA21_P": "J11",
"HA21_N": "J12",
"HA23_P": "L12",
"HA23_N": "L13",
}
),
("LPC", {
"GBTCLK0_M2C_P": "N8",
"GBTCLK0_M2C_N": "N7",
"LA01_CC_P": "AE23",
"LA01_CC_N": "AF23",
"LA05_P": "AG22",
"LA05_N": "AH22",
"LA09_P": "AK23",
"LA09_N": "AK24",
"LA13_P": "AB24",
"LA13_N": "AC25",
"LA17_CC_P": "AB27",
"LA17_CC_N": "AC27",
"LA23_P": "AH26",
"LA23_N": "AH27",
"LA26_P": "AK29",
"LA26_N": "AK30",
"CLK0_M2C_P": "AF22",
"CLK0_M2C_N": "AG23",
"LA02_P": "AF20",
"LA02_N": "AF21",
"LA04_P": "AH21",
"LA04_N": "AJ21",
"LA07_P": "AG25",
"LA07_N": "AH25",
"LA11_P": "AE25",
"LA11_N": "AF25",
"LA15_P": "AC24",
"LA15_N": "AD24",
"LA19_P": "AJ26",
"LA19_N": "AK26",
"LA21_P": "AG27",
"LA21_N": "AG28",
"LA24_P": "AG30",
"LA24_N": "AH30",
"LA28_P": "AE30",
"LA28_N": "AF30",
"LA30_P": "AB29",
"LA30_N": "AB30",
"LA32_P": "Y30",
"LA32_N": "AA30",
"LA06_P": "AK20",
"LA06_N": "AK21",
"LA10_P": "AJ24",
"LA10_N": "AK25",
"LA14_P": "AD21",
"LA14_N": "AE21",
"LA18_CC_P": "AD27",
"LA18_CC_N": "AD28",
"LA27_P": "AJ28",
"LA27_N": "AJ29",
"CLK1_M2C_P": "AG29",
"CLK1_M2C_N": "AH29",
"LA00_CC_P": "AD23",
"LA00_CC_N": "AE24",
"LA03_P": "AG20",
"LA03_N": "AH20",
"LA08_P": "AJ22",
"LA08_N": "AJ23",
"LA12_P": "AA20",
"LA12_N": "AB20",
"LA16_P": "AC22",
"LA16_N": "AD22",
"LA20_P": "AF26",
"LA20_N": "AF27",
"LA22_P": "AJ27",
"LA22_N": "AK28",
"LA25_P": "AC26",
"LA25_N": "AD26",
"LA29_P": "AE28",
"LA29_N": "AF28",
"LA31_P": "AD29",
"LA31_N": "AE29",
"LA33_P": "AC29",
"LA33_N": "AC30",
}
),
("XADC", {
"GPIO0": "AB25",
"GPIO1": "AA25",
"GPIO2": "AB28",
"GPIO3": "AA27",
"VAUX0_N": "J24",
"VAUX0_P": "J23",
"VAUX8_N": "L23",
"VAUX8_P": "L22",
}
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk156"
default_clk_period = 6.4
def __init__(self):
XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado")
self.add_platform_command("""
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 2.5 [current_design]
""")
self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
def create_programmer(self):
return VivadoProgrammer()
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
try:
self.add_period_constraint(self.lookup_request("clk200").p, 1e9/200e6)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("eth_clocks").rx, 1e9/125e6)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("eth_clocks").tx, 1e9/125e6)
except ConstraintError:
pass
self.add_platform_command("set_property DCI_CASCADE {{32 34}} [get_iobanks 33]")

498
litex_boards/official/platforms/kcu105.py Normal file
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@ -0,0 +1,498 @@
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
("user_led", 0, Pins("AP8"), IOStandard("LVCMOS18")),
("user_led", 1, Pins("H23"), IOStandard("LVCMOS18")),
("user_led", 2, Pins("P20"), IOStandard("LVCMOS18")),
("user_led", 3, Pins("P21"), IOStandard("LVCMOS18")),
("user_led", 4, Pins("N22"), IOStandard("LVCMOS18")),
("user_led", 5, Pins("M22"), IOStandard("LVCMOS18")),
("user_led", 6, Pins("R23"), IOStandard("LVCMOS18")),
("user_led", 7, Pins("P23"), IOStandard("LVCMOS18")),
("cpu_reset", 0, Pins("AN8"), IOStandard("LVCMOS18")),
("user_btn_c", 0, Pins("AE10"), IOStandard("LVCMOS18")),
("user_btn_n", 0, Pins("AD10"), IOStandard("LVCMOS18")),
("user_btn_s", 0, Pins("AF8"), IOStandard("LVCMOS18")),
("user_btn_w", 0, Pins("AF9"), IOStandard("LVCMOS18")),
("user_btn_e", 0, Pins("AE8"), IOStandard("LVCMOS18")),
("user_dip_btn", 0, Pins("AN16"), IOStandard("LVCMOS12")),
("user_dip_btn", 1, Pins("AN19"), IOStandard("LVCMOS12")),
("user_dip_btn", 2, Pins("AP18"), IOStandard("LVCMOS12")),
("user_dip_btn", 3, Pins("AN14"), IOStandard("LVCMOS12")),
("user_sma_clock", 0,
Subsignal("p", Pins("D23"), IOStandard("LVDS")),
Subsignal("n", Pins("C23"), IOStandard("LVDS"))
),
("user_sma_clock_p", 0, Pins("D23"), IOStandard("LVCMOS18")),
("user_sma_clock_n", 0, Pins("C23"), IOStandard("LVCMOS18")),
("user_sma_gpio", 0,
Subsignal("p", Pins("H27"), IOStandard("LVDS")),
Subsignal("n", Pins("G27"), IOStandard("LVDS"))
),
("user_sma_gpio_p", 0, Pins("H27"), IOStandard("LVCMOS18")),
("user_sma_gpio_n", 0, Pins("G27"), IOStandard("LVCMOS18")),
("clk125", 0,
Subsignal("p", Pins("G10"), IOStandard("LVDS")),
Subsignal("n", Pins("F10"), IOStandard("LVDS"))
),
("clk300", 0,
Subsignal("p", Pins("AK17"), IOStandard("DIFF_SSTL12")),
Subsignal("n", Pins("AK16"), IOStandard("DIFF_SSTL12"))
),
("i2c", 0,
Subsignal("scl", Pins("J24")),
Subsignal("sda", Pins("J25")),
IOStandard("LVCMOS18")
),
("serial", 0,
Subsignal("cts", Pins("L23")),
Subsignal("rts", Pins("K27")),
Subsignal("tx", Pins("K26")),
Subsignal("rx", Pins("G25")),
IOStandard("LVCMOS18")
),
("spiflash", 0, # clock needs to be accessed through primitive
Subsignal("cs_n", Pins("U7")),
Subsignal("dq", Pins("AC7 AB7 AA7 Y7")),
IOStandard("LVCMOS18")
),
("spiflash", 1, # clock needs to be accessed through primitive
Subsignal("cs_n", Pins("G26")),
Subsignal("dq", Pins("M20 L20 R21 R22")),
IOStandard("LVCMOS18")
),
("rotary", 0,
Subsignal("a", Pins("Y21")),
Subsignal("b", Pins("AD26")),
Subsignal("push", Pins("AF28")),
IOStandard("LVCMOS18")
),
("hdmi", 0,
Subsignal("d", Pins(
"AK11 AP11 AP13 AN13 AN11 AM11 AN12 AM12",
"AL12 AK12 AL13 AK13 AD11 AH12 AG12 AJ11",
"AG10 AK8")),
Subsignal("de", Pins("AE11")),
Subsignal("clk", Pins("AF13")),
Subsignal("vsync", Pins("AH13")),
Subsignal("hsync", Pins("AE13")),
Subsignal("spdif", Pins("AE12")),
Subsignal("spdif_out", Pins("AF12")),
IOStandard("LVCMOS18")
),
("ddram", 0,
Subsignal("a", Pins(
"AE17 AH17 AE18 AJ15 AG16 AL17 AK18 AG17",
"AF18 AH19 AF15 AD19 AJ14 AG19"),
IOStandard("SSTL12_DCI")),
Subsignal("ba", Pins("AF17 AL15"), IOStandard("SSTL12_DCI")),
Subsignal("bg", Pins("AG15"), IOStandard("SSTL12_DCI")),
Subsignal("ras_n", Pins("AF14"), IOStandard("SSTL12_DCI")), # A16
Subsignal("cas_n", Pins("AG14"), IOStandard("SSTL12_DCI")), # A15
Subsignal("we_n", Pins("AD16"), IOStandard("SSTL12_DCI")), # A14
Subsignal("cs_n", Pins("AL19"), IOStandard("SSTL12_DCI")),
Subsignal("act_n", Pins("AH14"), IOStandard("SSTL12_DCI")),
Subsignal("ten", Pins("AH16"), IOStandard("SSTL12_DCI")),
Subsignal("alert_n", Pins("AJ16"), IOStandard("SSTL12_DCI")),
Subsignal("par", Pins("AD18"), IOStandard("SSTL12_DCI")),
Subsignal("dm", Pins("AD21 AE25 AJ21 AM21 AH26 AN26 AJ29 AL32"),
IOStandard("POD12_DCI")),
Subsignal("dq", Pins(
"AE23 AG20 AF22 AF20 AE22 AD20 AG22 AE20",
"AJ24 AG24 AJ23 AF23 AH23 AF24 AH22 AG25",
"AL22 AL25 AM20 AK23 AK22 AL24 AL20 AL23",
"AM24 AN23 AN24 AP23 AP25 AN22 AP24 AM22",
"AH28 AK26 AK28 AM27 AJ28 AH27 AK27 AM26",
"AL30 AP29 AM30 AN28 AL29 AP28 AM29 AN27",
"AH31 AH32 AJ34 AK31 AJ31 AJ30 AH34 AK32",
"AN33 AP33 AM34 AP31 AM32 AN31 AL34 AN32",
),
IOStandard("POD12_DCI")),
Subsignal("dqs_p", Pins("AG21 AH24 AJ20 AP20 AL27 AN29 AH33 AN34"),
IOStandard("DIFF_POD12")),
Subsignal("dqs_n", Pins("AH21 AJ25 AK20 AP21 AL28 AP30 AJ33 AP34"),
IOStandard("DIFF_POD12")),
Subsignal("clk_p", Pins("AE16"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("clk_n", Pins("AE15"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("cke", Pins("AD15"), IOStandard("SSTL12_DCI")),
Subsignal("odt", Pins("AJ18"), IOStandard("SSTL12_DCI")),
Subsignal("reset_n", Pins("AL18"), IOStandard("LVCMOS12")),
Misc("SLEW=FAST"),
),
("pcie_x1", 0,
Subsignal("rst_n", Pins("K22"), IOStandard("LVCMOS18")),
Subsignal("clk_p", Pins("AB6")),
Subsignal("clk_n", Pins("AB5")),
Subsignal("rx_p", Pins("AB2")),
Subsignal("rx_n", Pins("AB1")),
Subsignal("tx_p", Pins("AC3")),
Subsignal("tx_n", Pins("AC4"))
),
("pcie_x2", 0,
Subsignal("rst_n", Pins("K22"), IOStandard("LVCMOS18")),
Subsignal("clk_p", Pins("AB6")),
Subsignal("clk_n", Pins("AB5")),
Subsignal("rx_p", Pins("AB2 AD2")),
Subsignal("rx_n", Pins("AB1 AD1")),
Subsignal("tx_p", Pins("AC3 AE4")),
Subsignal("tx_n", Pins("AC4 AE3"))
),
("pcie_x4", 0,
Subsignal("rst_n", Pins("K22"), IOStandard("LVCMOS18")),
Subsignal("clk_p", Pins("AB6")),
Subsignal("clk_n", Pins("AB5")),
Subsignal("rx_p", Pins("AB2 AD2 AF2 AH2")),
Subsignal("rx_n", Pins("AB1 AD1 AF1 AH1")),
Subsignal("tx_p", Pins("AC3 AE4 AG4 AH6")),
Subsignal("tx_n", Pins("AC4 AE3 AG3 AH5"))
),
("pcie_x8", 0,
Subsignal("rst_n", Pins("K22"), IOStandard("LVCMOS18")),
Subsignal("clk_p", Pins("AB6")),
Subsignal("clk_n", Pins("AB5")),
Subsignal("rx_p", Pins("AB2 AD2 AF2 AH2 AJ4 AK2 AM2 AP2")),
Subsignal("rx_n", Pins("AB1 AD1 AF1 AH1 AJ3 AK1 AM1 AP1")),
Subsignal("tx_p", Pins("AC3 AE4 AG4 AH6 AK6 AL4 AM6 AN4")),
Subsignal("tx_n", Pins("AC4 AE3 AG3 AH5 AK5 AL3 AM5 AN3"))
),
("sgmii_clock", 0,
Subsignal("p", Pins("P26"), IOStandard("LVDS_25")),
Subsignal("n", Pins("N26"), IOStandard("LVDS_25"))
),
("si570_refclk", 0,
Subsignal("p", Pins("P6")),
Subsignal("n", Pins("P5"))
),
("user_sma_mgt_refclk", 0,
Subsignal("p", Pins("V6")),
Subsignal("n", Pins("V5"))
),
("user_sma_mgt_tx", 0,
Subsignal("p", Pins("R4")),
Subsignal("n", Pins("R3"))
),
("user_sma_mgt_rx", 0,
Subsignal("p", Pins("P2")),
Subsignal("n", Pins("P1"))
),
("sfp", 0,
Subsignal("txp", Pins("U4")),
Subsignal("txn", Pins("U3")),
Subsignal("rxp", Pins("T2")),
Subsignal("rxn", Pins("T1"))
),
("sfp_tx", 0,
Subsignal("p", Pins("U4")),
Subsignal("n", Pins("U3")),
),
("sfp_rx", 0,
Subsignal("p", Pins("T2")),
Subsignal("n", Pins("T1")),
),
("sfp_tx_disable_n", 0, Pins("AL8"), IOStandard("LVCMOS18")),
("sfp", 1,
Subsignal("txp", Pins("W4")),
Subsignal("txn", Pins("W3")),
Subsignal("rxp", Pins("V2")),
Subsignal("rxn", Pins("V1"))
),
("sfp_tx", 1,
Subsignal("p", Pins("W4")),
Subsignal("n", Pins("W3")),
),
("sfp_rx", 1,
Subsignal("p", Pins("V2")),
Subsignal("n", Pins("V1")),
),
("sfp_tx_disable_n", 1, Pins("D28"), IOStandard("LVCMOS18")),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
("HPC", {
"DP0_C2M_P": "F6",
"DP0_C2M_N": "F5",
"DP0_M2C_P": "E4",
"DP0_M2C_N": "E3",
"DP1_C2M_P": "D6",
"DP1_C2M_N": "D5",
"DP1_M2C_P": "D2",
"DP1_M2C_N": "D1",
"DP2_C2M_P": "C4",
"DP2_C2M_N": "C3",
"DP2_M2C_P": "B2",
"DP2_M2C_N": "B1",
"DP3_C2M_P": "B6",
"DP3_C2M_N": "B5",
"DP3_M2C_P": "A4",
"DP3_M2C_N": "A3",
"DP4_C2M_P": "N4",
"DP4_C2M_N": "N3",
"DP4_M2C_P": "M2",
"DP4_M2C_N": "M1",
"DP5_C2M_P": "J4",
"DP5_C2M_N": "J3",
"DP5_M2C_P": "H2",
"DP5_M2C_N": "H1",
"DP6_C2M_P": "L4",
"DP6_C2M_N": "L3",
"DP6_M2C_P": "K2",
"DP6_M2C_N": "K1",
"DP7_C2M_P": "G4",
"DP7_C2M_N": "G3",
"DP7_M2C_P": "F2",
"DP7_M2C_N": "F1",
"LA06_P": "D13",
"LA06_N": "C13",
"LA10_P": "L8",
"LA10_N": "K8",
"LA14_P": "B10",
"LA14_N": "A10",
"LA18_CC_P": "E22",
"LA18_CC_N": "E23",
"LA27_P": "H21",
"LA27_N": "G21",
"HA01_CC_P": "E16",
"HA01_CC_N": "D16",
"HA05_P": "J15",
"HA05_N": "J14",
"HA09_P": "F18",
"HA09_N": "F17",
"HA13_P": "B14",
"HA13_N": "A14",
"HA16_P": "A19",
"HA16_N": "A18",
"HA20_P": "C19",
"HA20_N": "B19",
"CLK1_M2C_P": "E25",
"CLK1_M2C_N": "D25",
"LA00_CC_P": "H11",
"LA00_CC_N": "G11",
"LA03_P": "A13",
"LA03_N": "A12",
"LA08_P": "J8",
"LA08_N": "H8",
"LA12_P": "E10",
"LA12_N": "D10",
"LA16_P": "B9",
"LA16_N": "A9",
"LA20_P": "B24",
"LA20_N": "A24",
"LA22_P": "G24",
"LA22_N": "F25",
"LA25_P": "D20",
"LA25_N": "D21",
"LA29_P": "B20",
"LA29_N": "A20",
"LA31_P": "B25",
"LA31_N": "A25",
"LA33_P": "A27",
"LA33_N": "A28",
"HA03_P": "G15",
"HA03_N": "G14",
"HA07_P": "L19",
"HA07_N": "L18",
"HA11_P": "J19",
"HA11_N": "J18",
"HA14_P": "F15",
"HA14_N": "F14",
"HA18_P": "B17",
"HA18_N": "B16",
"HA22_P": "C18",
"HA22_N": "C17",
"GBTCLK1_M2C_P": "H6",
"GBTCLK1_M2C_N": "H5",
"GBTCLK0_M2C_P": "K6",
"GBTCLK0_M2C_N": "K5",
"LA01_CC_P": "G9",
"LA01_CC_N": "F9",
"LA05_P": "L13",
"LA05_N": "K13",
"LA09_P": "J9",
"LA09_N": "H9",
"LA13_P": "D9",
"LA13_N": "C9",
"LA17_CC_P": "D24",
"LA17_CC_N": "C24",
"LA23_P": "G22",
"LA23_N": "F22",
"LA26_P": "G20",
"LA26_N": "F20",
"PG_M2C": "L27",
"HA00_CC_P": "G17",
"HA00_CC_N": "G16",
"HA04_P": "G19",
"HA04_N": "F19",
"HA08_P": "K18",
"HA08_N": "K17",
"HA12_P": "K16",
"HA12_N": "J16",
"HA15_P": "D14",
"HA15_N": "C14",
"HA19_P": "D19",
"HA19_N": "D18",
"PRSNT_M2C_B": "H24",
"CLK0_M2C_P": "H12",
"CLK0_M2C_N": "G12",
"LA02_P": "K10",
"LA02_N": "J10",
"LA04_P": "L12",
"LA04_N": "K12",
"LA07_P": "F8",
"LA07_N": "E8",
"LA11_P": "K11",
"LA11_N": "J11",
"LA15_P": "D8",
"LA15_N": "C8",
"LA19_P": "C21",
"LA19_N": "C22",
"LA21_P": "F23",
"LA21_N": "F24",
"LA24_P": "E20",
"LA24_N": "E21",
"LA28_P": "B21",
"LA28_N": "B22",
"LA30_P": "C26",
"LA30_N": "B26",
"LA32_P": "E26",
"LA32_N": "D26",
"HA02_P": "H19",
"HA02_N": "H18",
"HA06_P": "L15",
"HA06_N": "K15",
"HA10_P": "H17",
"HA10_N": "H16",
"HA17_CC_P": "E18",
"HA17_CC_N": "E17",
"HA21_P": "E15",
"HA21_N": "D15",
"HA23_P": "B15",
"HA23_N": "A15",
}
),
("LPC", {
"GBTCLK0_M2C_P": "AA24",
"GBTCLK0_M2C_N": "AA25",
"LA01_CC_P": "W25",
"LA01_CC_N": "Y25",
"LA05_P": "V27",
"LA05_N": "V28",
"LA09_P": "V26",
"LA09_N": "W26",
"LA13_P": "AA20",
"LA13_N": "AB20",
"LA17_CC_P": "AA32",
"LA17_CC_N": "AB32",
"LA23_P": "AD30",
"LA23_N": "AD31",
"LA26_P": "AF33",
"LA26_N": "AG34",
"CLK0_M2C_P": "AA24",
"CLK0_M2C_N": "AA25",
"LA02_P": "AA22",
"LA02_N": "AB22",
"LA04_P": "U26",
"LA04_N": "U27",
"LA07_P": "V22",
"LA07_N": "V23",
"LA11_P": "V21",
"LA11_N": "W21",
"LA15_P": "AB25",
"LA15_N": "AB26",
"LA19_P": "AA29",
"LA19_N": "AB29",
"LA21_P": "AC33",
"LA21_N": "AD33",
"LA24_P": "AE32",
"LA24_N": "AF32",
"LA28_P": "V31",
"LA28_N": "W31",
"LA30_P": "Y31",
"LA30_N": "Y32",
"LA32_P": "W30",
"LA32_N": "Y30",
"LA06_P": "V29",
"LA06_N": "W29",
"LA10_P": "T22",
"LA10_N": "T23",
"LA14_P": "U21",
"LA14_N": "U22",
"LA18_CC_P": "AB30",
"LA18_CC_N": "AB31",
"LA27_P": "AG31",
"LA27_N": "AG32",
"CLK1_M2C_P": "AC31",
"CLK1_M2C_N": "AC32",
"LA00_CC_P": "W23",
"LA00_CC_N": "W24",
"LA03_P": "W28",
"LA03_N": "Y28",
"LA08_P": "U24",
"LA08_N": "U25",
"LA12_P": "AC22",
"LA12_N": "AC23",
"LA16_P": "AB21",
"LA16_N": "AC21",
"LA20_P": "AA34",
"LA20_N": "AB34",
"LA22_P": "AC34",
"LA22_N": "AD34",
"LA25_P": "AE33",
"LA25_N": "AF34",
"LA29_P": "U34",
"LA29_N": "V34",
"LA31_P": "V33",
"LA31_N": "W34",
"LA33_P": "W33",
"LA33_N": "Y33",
}
)
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk125"
default_clk_period = 8.0
def __init__(self):
XilinxPlatform.__init__(self, "xcku040-ffva1156-2-e", _io, _connectors, toolchain="vivado")
def create_programmer(self):
return VivadoProgrammer()
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 44]")
self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 45]")
self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 46]")

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litex_boards/official/platforms/machxo3.py Normal file
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# This file is Copyright (c) 2016 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
from litex.build.lattice.programmer import LatticeProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
("clk12", 0, Pins("C8"), IOStandard("LVCMOS33")),
("rst_n", 0, Pins("B3"), IOStandard("LVCMOS33")),
("user_led", 0, Pins("H11"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("J13"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("J11"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("L12"), IOStandard("LVCMOS33")),
("user_led", 4, Pins("K11"), IOStandard("LVCMOS33")),
("user_led", 5, Pins("L13"), IOStandard("LVCMOS33")),
("user_led", 6, Pins("N15"), IOStandard("LVCMOS33")),
("user_led", 7, Pins("P16"), IOStandard("LVCMOS33")),
("user_dip_btn", 0, Pins("N2"), IOStandard("LVCMOS33")),
("user_dip_btn", 1, Pins("P1"), IOStandard("LVCMOS33")),
("user_dip_btn", 2, Pins("M3"), IOStandard("LVCMOS33")),
("user_dip_btn", 3, Pins("N1"), IOStandard("LVCMOS33")),
("serial", 0,
Subsignal("tx", Pins("C11"), IOStandard("LVCMOS33")),
Subsignal("rx", Pins("A11"), IOStandard("LVCMOS33")),
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticePlatform):
default_clk_name = "clk12"
default_clk_period = 83
def __init__(self):
LatticePlatform.__init__(self, "LCMXO3L-6900C-5BG256C", _io)
def create_programmer(self):
_xcf_template = """
<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
<ispXCF version="3.6.0">
<Comment></Comment>
<Chain>
<Comm>JTAG</Comm>
<Device>
<SelectedProg value="TRUE"/>
<Pos>1</Pos>
<Vendor>Lattice</Vendor>
<Family>MachXO3L</Family>
<Name>LCMXO3L-6900C</Name>
<IDCode>0x412bd043</IDCode>
<Package>All</Package>
<PON>LCMXO3L-6900C</PON>
<Bypass>
<InstrLen>8</InstrLen>
<InstrVal>11111111</InstrVal>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
<File>{bitstream_file}</File>
<JedecChecksum>N/A</JedecChecksum>
<Operation>SRAM Fast Configuration</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<IOState>HighZ</IOState>
<PreloadLength>664</PreloadLength>
<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
<Usercode>0x00000000</Usercode>
<AccessMode>SRAM</AccessMode>
</Option>
</Device>
</Chain>
<ProjectOptions>
<Program>SEQUENTIAL</Program>
<Process>ENTIRED CHAIN</Process>
<OperationOverride>No Override</OperationOverride>
<StartTAP>TLR</StartTAP>
<EndTAP>TLR</EndTAP>
<VerifyUsercode value="FALSE"/>
</ProjectOptions>
<CableOptions>
<CableName>USB2</CableName>
<PortAdd>FTUSB-0</PortAdd>
<USBID>Lattice XO3L Starter Kit A Location 0000 Serial A</USBID>
</CableOptions>
</ispXCF>
"""
return LatticeProgrammer(_xcf_template)

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# This file is Copyright (c) 2015 Matt O'Gorman <mog@rldn.net>
# License: BSD
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.build.xilinx.programmer import FpgaProg
# IOs ----------------------------------------------------------------------------------------------
_io = [
("user_led", 0, Pins("P11"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("N9"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("M9"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("P9"), IOStandard("LVCMOS33")),
("user_led", 4, Pins("T8"), IOStandard("LVCMOS33")),
("user_led", 5, Pins("N8"), IOStandard("LVCMOS33")),
("user_led", 6, Pins("P8"), IOStandard("LVCMOS33")),
("user_led", 7, Pins("P7"), IOStandard("LVCMOS33")),
("user_sw", 0, Pins("L1"), IOStandard("LVCMOS33"), Misc("PULLUP")),
("user_sw", 1, Pins("L3"), IOStandard("LVCMOS33"), Misc("PULLUP")),
("user_sw", 2, Pins("L4"), IOStandard("LVCMOS33"), Misc("PULLUP")),
("user_sw", 3, Pins("L5"), IOStandard("LVCMOS33"), Misc("PULLUP")),
("clk32", 0, Pins("J4"), IOStandard("LVCMOS33")),
("clk50", 0, Pins("K3"), IOStandard("LVCMOS33")),
("spiflash", 0,
Subsignal("cs_n", Pins("T3"), IOStandard("LVCMOS33")),
Subsignal("clk", Pins("R11"), IOStandard("LVCMOS33")),
Subsignal("mosi", Pins("T10"), IOStandard("LVCMOS33")),
Subsignal("miso", Pins("P10"), IOStandard("LVCMOS33"))
),
("adc", 0,
Subsignal("cs_n", Pins("F6"), IOStandard("LVCMOS33")),
Subsignal("clk", Pins("G6"), IOStandard("LVCMOS33")),
Subsignal("mosi", Pins("H4"), IOStandard("LVCMOS33")),
Subsignal("miso", Pins("H5"), IOStandard("LVCMOS33"))
),
("serial", 0,
Subsignal("tx", Pins("N6"), IOStandard("LVCMOS33")), # FTDI D1
Subsignal("rx", Pins("M7"), IOStandard("LVCMOS33")) # FTDI D0
),
("audio", 0,
Subsignal("a0", Pins("B8"), IOStandard("LVCMOS33")),
Subsignal("a1", Pins("A8"), IOStandard("LVCMOS33"))
),
("sdram_clock", 0, Pins("G16"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
("sdram", 0,
Subsignal("a", Pins("T15 R16 P15 P16 N16 M15 M16 L16 K15 K16 R15 J16 H15")),
Subsignal("dq", Pins("T13 T12 R12 T9 R9 T7 R7 T6 F16 E15 E16 D16 B16 B15 C16 C15")),
Subsignal("we_n", Pins("R5")),
Subsignal("ras_n", Pins("R2")),
Subsignal("cas_n", Pins("T4")),
Subsignal("cs_n", Pins("R1")),
Subsignal("cke", Pins("H16")),
Subsignal("ba", Pins("R14 T14")),
Subsignal("dm", Pins("T5 F15")),
IOStandard("LVCMOS33"), Misc("SLEW=FAST")
),
("usb_fifo", 0,
Subsignal("data", Pins("M7 N6 M6 P5 N5 P4 P2 P1")),
Subsignal("rxf_n", Pins("N3")),
Subsignal("txe_n", Pins("N1")),
Subsignal("rd_n", Pins("M1")),
Subsignal("wr_n", Pins("M2")),
Subsignal("siwua", Pins("M3")),
IOStandard("LVCMOS33"), Drive(8), Misc("SLEW=FAST")
),
("sd", 0,
Subsignal("sck", Pins("L12")),
Subsignal("d3", Pins("K12")),
Subsignal("d", Pins("M10")),
Subsignal("d1", Pins("L10")),
Subsignal("d2", Pins("J11")),
Subsignal("cmd", Pins("K11")),
IOStandard("LVCMOS33")
),
("dvi_in", 0,
Subsignal("clk_p", Pins("C9"), IOStandard("TMDS_33")),
Subsignal("clk_n", Pins("A9"), IOStandard("TMDS_33")),
Subsignal("data_p", Pins("C7 B6 B5"), IOStandard("TMDS_33")),
Subsignal("data_n", Pins("A7 A6 A5"), IOStandard("TMDS_33")),
Subsignal("scl", Pins("C1"), IOStandard("LVCMOS33")),
Subsignal("sda", Pins("B1"), IOStandard("LVCMOS33"))
),
("dvi_out", 0,
Subsignal("clk_p", Pins("B14"), IOStandard("TMDS_33")),
Subsignal("clk_n", Pins("A14"), IOStandard("TMDS_33")),
Subsignal("data_p", Pins("C13 B12 C11"), IOStandard("TMDS_33")),
Subsignal("data_n", Pins("A13 A12 A11"), IOStandard("TMDS_33")),
)
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
("A", "E7 C8 D8 E8 D9 A10 B10 C10 E10 F9 F10 D11"),
("B", "E11 D14 D12 E12 E13 F13 F12 F14 G12 H14 J14"),
("C", "J13 J12 K14 L14 L13 M14 M13 N14 M12 N12 P12 M11"),
("D", "D6 C6 E6 C5"),
("E", "D5 A4 G5 A3 B3 A2 B2 C3 C2 D3 D1 E3"),
("F", "E2 E1 E4 F4 F5 G3 F3 G1 H3 H1 H2 J1")
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk32"
default_clk_period = 31.25
def __init__(self, device="xc6slx25"):
XilinxPlatform.__init__(self, device+"-3-ftg256", _io, _connectors)
def create_programmer(self):
return FpgaProg()

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litex_boards/official/platforms/netv2.py Normal file
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from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
# clock
("clk50", 0, Pins("J19"), IOStandard("LVCMOS33")),
# leds
("user_led", 0, Pins("M21"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("N20"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("L21"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("AA21"), IOStandard("LVCMOS33")),
("user_led", 4, Pins("R19"), IOStandard("LVCMOS33")),
("user_led", 5, Pins("M16"), IOStandard("LVCMOS33")),
# flash
("flash", 0,
Subsignal("cs_n", Pins("T19")),
Subsignal("mosi", Pins("P22")),
Subsignal("miso", Pins("R22")),
Subsignal("vpp", Pins("P21")),
Subsignal("hold", Pins("R21")),
IOStandard("LVCMOS33")
),
# serial
("serial", 0,
Subsignal("tx", Pins("E14")),
Subsignal("rx", Pins("E13")),
IOStandard("LVCMOS33"),
),
# dram
("ddram", 0,
Subsignal("a", Pins(
"U6 V4 W5 V5 AA1 Y2 AB1 AB3",
"AB2 Y3 W6 Y1 V2 AA3"
),
IOStandard("SSTL15")),
Subsignal("ba", Pins("U5 W4 V7"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("Y9"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("Y7"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("V8"), IOStandard("SSTL15")),
Subsignal("dm", Pins("M5 L3"), IOStandard("SSTL15")),
Subsignal("dq", Pins(
"N2 M6 P1 N5 P2 N4 R1 P6 "
"K3 M2 K4 M3 J6 L5 J4 K6 "
),
IOStandard("SSTL15"),
Misc("IN_TERM=UNTUNED_SPLIT_50")),
Subsignal("dqs_p", Pins("P5 M1"), IOStandard("DIFF_SSTL15")),
Subsignal("dqs_n", Pins("P4 L1"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_p", Pins("R3"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_n", Pins("R2"), IOStandard("DIFF_SSTL15")),
Subsignal("cke", Pins("Y8"), IOStandard("SSTL15")),
Subsignal("odt", Pins("W9"), IOStandard("SSTL15")),
Subsignal("reset_n", Pins("AB5"), IOStandard("LVCMOS15")),
Subsignal("cs_n", Pins("V9"), IOStandard("SSTL15")),
Misc("SLEW=FAST"),
),
# ethernet
("eth_clocks", 0,
Subsignal("ref_clk", Pins("D17")),
IOStandard("LVCMOS33"),
),
("eth", 0,
Subsignal("rst_n", Pins("F16")),
Subsignal("rx_data", Pins("A20 B18")),
Subsignal("crs_dv", Pins("C20")),
Subsignal("tx_en", Pins("A19")),
Subsignal("tx_data", Pins("C18 C19")),
Subsignal("mdc", Pins("F14")),
Subsignal("mdio", Pins("F13")),
Subsignal("rx_er", Pins("B20")),
Subsignal("int_n", Pins("D21")),
IOStandard("LVCMOS33")
),
# sdcard
("sdcard", 0,
Subsignal("data", Pins("L15 L16 K14 M13"), Misc("PULLUP True")),
Subsignal("cmd", Pins("L13"), Misc("PULLUP True")),
Subsignal("clk", Pins("K18")),
IOStandard("LVCMOS33"), Misc("SLEW=FAST")
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk50"
default_clk_period = 20.0
def __init__(self):
XilinxPlatform.__init__(self, "xc7a35t-fgg484-2", _io, toolchain="vivado")

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# This file is Copyright (c) 2018 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
("user_led", 0, Pins("H17"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("K15"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("J13"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("N14"), IOStandard("LVCMOS33")),
("user_led", 4, Pins("R18"), IOStandard("LVCMOS33")),
("user_led", 5, Pins("V17"), IOStandard("LVCMOS33")),
("user_led", 6, Pins("U17"), IOStandard("LVCMOS33")),
("user_led", 7, Pins("U16"), IOStandard("LVCMOS33")),
("user_led", 8, Pins("V16"), IOStandard("LVCMOS33")),
("user_led", 9, Pins("T15"), IOStandard("LVCMOS33")),
("user_led", 10, Pins("U14"), IOStandard("LVCMOS33")),
("user_led", 11, Pins("T16"), IOStandard("LVCMOS33")),
("user_led", 12, Pins("V15"), IOStandard("LVCMOS33")),
("user_led", 13, Pins("V14"), IOStandard("LVCMOS33")),
("user_led", 14, Pins("V12"), IOStandard("LVCMOS33")),
("user_led", 15, Pins("V11"), IOStandard("LVCMOS33")),
("user_sw", 0, Pins("J15"), IOStandard("LVCMOS33")),
("user_sw", 1, Pins("L16"), IOStandard("LVCMOS33")),
("user_sw", 2, Pins("M13"), IOStandard("LVCMOS33")),
("user_sw", 3, Pins("R15"), IOStandard("LVCMOS33")),
("user_sw", 4, Pins("R17"), IOStandard("LVCMOS33")),
("user_sw", 5, Pins("T18"), IOStandard("LVCMOS33")),
("user_sw", 6, Pins("U18"), IOStandard("LVCMOS33")),
("user_sw", 7, Pins("R13"), IOStandard("LVCMOS33")),
("user_sw", 8, Pins("T8"), IOStandard("LVCMOS33")),
("user_sw", 9, Pins("U8"), IOStandard("LVCMOS33")),
("user_sw", 10, Pins("R16"), IOStandard("LVCMOS33")),
("user_sw", 11, Pins("T13"), IOStandard("LVCMOS33")),
("user_sw", 12, Pins("H6"), IOStandard("LVCMOS33")),
("user_sw", 13, Pins("U12"), IOStandard("LVCMOS33")),
("user_sw", 14, Pins("U11"), IOStandard("LVCMOS33")),
("user_sw", 15, Pins("V10"), IOStandard("LVCMOS33")),
("user_btn", 0, Pins("N17"), IOStandard("LVCMOS33")),
("user_btn", 1, Pins("P18"), IOStandard("LVCMOS33")),
("user_btn", 2, Pins("P17"), IOStandard("LVCMOS33")),
("user_btn", 3, Pins("M17"), IOStandard("LVCMOS33")),
("user_btn", 4, Pins("M18"), IOStandard("LVCMOS33")),
("clk100", 0, Pins("E3"), IOStandard("LVCMOS33")),
("cpu_reset", 0, Pins("C12"), IOStandard("LVCMOS33")),
("serial", 0,
Subsignal("tx", Pins("D4")),
Subsignal("rx", Pins("C4")),
IOStandard("LVCMOS33"),
),
("ddram", 0,
Subsignal("a", Pins(
"M4 P4 M6 T1 L3 P5 M2 N1",
"L4 N5 R2 K5 N6"),
IOStandard("SSTL18_II")),
Subsignal("ba", Pins("P2 P3 R1"), IOStandard("SSTL18_II")),
Subsignal("ras_n", Pins("N4"), IOStandard("SSTL18_II")),
Subsignal("cas_n", Pins("L1"), IOStandard("SSTL18_II")),
Subsignal("we_n", Pins("N2"), IOStandard("SSTL18_II")),
Subsignal("dm", Pins("T6 U1"), IOStandard("SSTL18_II")),
Subsignal("dq", Pins(
"R7 V6 R8 U7 V7 R6 U6 R5",
"T5 U3 V5 U4 V4 T4 V1 T3"),
IOStandard("SSTL18_II"),
Misc("IN_TERM=UNTUNED_SPLIT_50")),
Subsignal("dqs_p", Pins("U9 U2"), IOStandard("DIFF_SSTL18_II")),
Subsignal("dqs_n", Pins("V9 V2"), IOStandard("DIFF_SSTL18_II")),
Subsignal("clk_p", Pins("L6"), IOStandard("DIFF_SSTL18_II")),
Subsignal("clk_n", Pins("L5"), IOStandard("DIFF_SSTL18_II")),
Subsignal("cke", Pins("M1"), IOStandard("SSTL18_II")),
Subsignal("odt", Pins("M3"), IOStandard("SSTL18_II")),
Subsignal("cs_n", Pins("K6"), IOStandard("SSTL18_II")),
Misc("SLEW=FAST"),
),
("eth_clocks", 0,
Subsignal("ref_clk", Pins("D5")),
IOStandard("LVCMOS33"),
),
("eth", 0,
Subsignal("rst_n", Pins("B3")),
Subsignal("rx_data", Pins("C11 D10")),
Subsignal("crs_dv", Pins("D9")),
Subsignal("tx_en", Pins("B9")),
Subsignal("tx_data", Pins("A10 A8")),
Subsignal("mdc", Pins("C9")),
Subsignal("mdio", Pins("A9")),
Subsignal("rx_er", Pins("C10")),
Subsignal("int_n", Pins("D8")),
IOStandard("LVCMOS33")
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 10.0
def __init__(self):
XilinxPlatform.__init__(self, "xc7a100t-CSG324-1", _io, toolchain="vivado")
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
def create_programmer(self):
return VivadoProgrammer()
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)

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# This file is Copyright (c) 2015 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
("user_led", 0, Pins("T14"), IOStandard("LVCMOS25")),
("user_led", 1, Pins("T15"), IOStandard("LVCMOS25")),
("user_led", 2, Pins("T16"), IOStandard("LVCMOS25")),
("user_led", 3, Pins("U16"), IOStandard("LVCMOS25")),
("user_led", 4, Pins("V15"), IOStandard("LVCMOS25")),
("user_led", 5, Pins("W16"), IOStandard("LVCMOS25")),
("user_led", 6, Pins("W15"), IOStandard("LVCMOS25")),
("user_led", 7, Pins("Y13"), IOStandard("LVCMOS25")),
("user_sw", 0, Pins("E22"), IOStandard("LVCMOS25")),
("user_sw", 1, Pins("F21"), IOStandard("LVCMOS25")),
("user_sw", 2, Pins("G21"), IOStandard("LVCMOS25")),
("user_sw", 3, Pins("G22"), IOStandard("LVCMOS25")),
("user_sw", 4, Pins("H17"), IOStandard("LVCMOS25")),
("user_sw", 5, Pins("J16"), IOStandard("LVCMOS25")),
("user_sw", 6, Pins("K13"), IOStandard("LVCMOS25")),
("user_sw", 7, Pins("M17"), IOStandard("LVCMOS25")),
("user_btn", 0, Pins("B22"), IOStandard("LVCMOS25")),
("user_btn", 1, Pins("D22"), IOStandard("LVCMOS25")),
("user_btn", 2, Pins("C22"), IOStandard("LVCMOS25")),
("user_btn", 3, Pins("D14"), IOStandard("LVCMOS25")),
("user_btn", 4, Pins("F15"), IOStandard("LVCMOS25")),
("user_btn", 5, Pins("G4"), IOStandard("LVCMOS25")),
("vadj", 0, Pins("AA13 AB17"), IOStandard("LVCMOS25")),
("oled", 0,
Subsignal("dc", Pins("W22")),
Subsignal("res", Pins("U21")),
Subsignal("sclk", Pins("W21")),
Subsignal("sdin", Pins("Y22")),
Subsignal("vbat", Pins("P20")),
Subsignal("vdd", Pins("V22")),
IOStandard("LVCMOS33")
),
("clk100", 0, Pins("R4"), IOStandard("LVCMOS33")),
("cpu_reset", 0, Pins("G4"), IOStandard("LVCMOS15")),
("serial", 0,
Subsignal("tx", Pins("AA19")),
Subsignal("rx", Pins("V18")),
IOStandard("LVCMOS33"),
),
("ddram", 0,
Subsignal("a", Pins(
"M2 M5 M3 M1 L6 P1 N3 N2",
"M6 R1 L5 N5 N4 P2 P6"),
IOStandard("SSTL15")),
Subsignal("ba", Pins("L3 K6 L4"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("J4"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("K3"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("L1"), IOStandard("SSTL15")),
Subsignal("dm", Pins("G3 F1"), IOStandard("SSTL15")),
Subsignal("dq", Pins(
"G2 H4 H5 J1 K1 H3 H2 J5",
"E3 B2 F3 D2 C2 A1 E2 B1"),
IOStandard("SSTL15"),
Misc("IN_TERM=UNTUNED_SPLIT_50")),
Subsignal("dqs_p", Pins("K2 E1"), IOStandard("DIFF_SSTL15")),
Subsignal("dqs_n", Pins("J2 D1"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_p", Pins("P5"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_n", Pins("P4"), IOStandard("DIFF_SSTL15")),
Subsignal("cke", Pins("J6"), IOStandard("SSTL15")),
Subsignal("odt", Pins("K4"), IOStandard("SSTL15")),
Subsignal("reset_n", Pins("G1"), IOStandard("SSTL15")),
Misc("SLEW=FAST"),
),
("eth_clocks", 0,
Subsignal("tx", Pins("AA14")),
Subsignal("rx", Pins("V13")),
IOStandard("LVCMOS25")
),
("eth", 0,
Subsignal("rst_n", Pins("U7"), IOStandard("LVCMOS33")),
Subsignal("int_n", Pins("Y14")),
Subsignal("mdio", Pins("Y16")),
Subsignal("mdc", Pins("AA16")),
Subsignal("rx_ctl", Pins("W10")),
Subsignal("rx_data", Pins("AB16 AA15 AB15 AB11")),
Subsignal("tx_ctl", Pins("V10")),
Subsignal("tx_data", Pins("Y12 W12 W11 Y11")),
IOStandard("LVCMOS25")
),
("hdmi_in", 0,
Subsignal("clk_p", Pins("V4"), IOStandard("TMDS_33")),
Subsignal("clk_n", Pins("W4"), IOStandard("TMDS_33")),
Subsignal("data0_p", Pins("Y3"), IOStandard("TMDS_33")),
Subsignal("data0_n", Pins("AA3"), IOStandard("TMDS_33")),
Subsignal("data1_p", Pins("W2"), IOStandard("TMDS_33")),
Subsignal("data1_n", Pins("Y2"), IOStandard("TMDS_33")),
Subsignal("data2_p", Pins("U2"), IOStandard("TMDS_33")),
Subsignal("data2_n", Pins("V2"), IOStandard("TMDS_33")),
Subsignal("scl", Pins("Y4"), IOStandard("LVCMOS33")),
Subsignal("sda", Pins("AB5"), IOStandard("LVCMOS33")),
Subsignal("hpd_en", Pins("AB12"), IOStandard("LVCMOS25")),
Subsignal("cec", Pins("AA5"), IOStandard("LVCMOS33")), # FIXME
Subsignal("txen", Pins("R3"), IOStandard("LVCMOS33")), # FIXME
),
("hdmi_out", 0,
Subsignal("clk_p", Pins("T1"), IOStandard("TMDS_33")),
Subsignal("clk_n", Pins("U1"), IOStandard("TMDS_33")),
Subsignal("data0_p", Pins("W1"), IOStandard("TMDS_33")),
Subsignal("data0_n", Pins("Y1"), IOStandard("TMDS_33")),
Subsignal("data1_p", Pins("AA1"), IOStandard("TMDS_33")),
Subsignal("data1_n", Pins("AB1"), IOStandard("TMDS_33")),
Subsignal("data2_p", Pins("AB3"), IOStandard("TMDS_33")),
Subsignal("data2_n", Pins("AB2"), IOStandard("TMDS_33")),
Subsignal("scl", Pins("U3"), IOStandard("LVCMOS33")),
Subsignal("sda", Pins("V3"), IOStandard("LVCMOS33")),
Subsignal("cec", Pins("AA4"), IOStandard("LVCMOS33")), # FIXME
Subsignal("hdp", Pins("AB13"), IOStandard("LVCMOS25")), # FIXME
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
("LPC", {
"DP0_C2M_P": "D7",
"DP0_C2M_N": "C7",
"DP0_M2C_P": "D9",
"DP0_M2C_N": "C9",
"GBTCLK0_M2C_P": "F10",
"GBTCLK0_M2C_N": "E10",
"LA01_CC_P": "J20",
"LA01_CC_N": "J21",
"LA05_P": "M21",
"LA05_N": "L21",
"LA09_P": "H20",
"LA09_N": "G20",
"LA13_P": "K17",
"LA13_N": "J17",
"LA17_CC_P": "B17",
"LA17_CC_N": "B18",
"LA23_P": "B21",
"LA23_N": "A21",
"LA26_P": "F18",
"LA26_N": "E18",
"CLK0_M2C_P": "J19",
"CLK0_M2C_N": "A19",
"LA02_P": "M18",
"LA02_N": "L18",
"LA04_P": "N20",
"LA04_N": "M20",
"LA07_P": "M13",
"LA07_N": "L13",
"LA11_P": "L14",
"LA11_N": "L15",
"LA15_P": "L16",
"LA15_N": "K16",
"LA19_P": "A18",
"LA19_N": "A19",
"LA21_P": "E19",
"LA21_N": "D19",
"LA24_P": "B15",
"LA24_N": "B16",
"LA28_P": "C13",
"LA28_N": "B13",
"LA30_P": "A13",
"LA30_N": "A14",
"LA32_P": "A15",
"LA32_N": "A16",
"LA06_P": "N22",
"LA06_N": "M22",
"LA10_P": "K21",
"LA10_N": "K22",
"LA14_P": "J22",
"LA14_N": "H22",
"LA18_CC_P": "D17",
"LA18_CC_N": "C17",
"LA27_P": "B20",
"LA27_N": "A20",
"CLK1_M2C_P": "C18",
"CLK1_M2C_N": "C19",
"LA00_CC_P": "K18",
"LA00_CC_N": "K19",
"LA03_P": "N18",
"LA03_N": "N19",
"LA08_P": "M15",
"LA08_N": "M16",
"LA12_P": "L19",
"LA12_N": "L20",
"LA16_P": "G17",
"LA16_N": "G18",
"LA20_P": "F19",
"LA20_N": "F20",
"LA22_P": "E21",
"LA22_N": "D21",
"LA25_P": "F16",
"LA25_N": "E17",
"LA29_P": "C14",
"LA29_N": "C15",
"LA31_P": "E13",
"LA31_N": "E14",
"LA33_P": "F13",
"LA33_N": "F14",
}
)
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 10.0
def __init__(self):
XilinxPlatform.__init__(self, "xc7a200t-sbg484-1", _io, _connectors, toolchain="vivado")
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 35]")
def create_programmer(self):
return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
try:
self.add_period_constraint(self.lookup_request("eth_clocks").rx, 1e9/125e6)
except ConstraintError:
pass

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# This file is Copyright (c) 2019 Michael Betz <michibetz@gmail.com>
# License: BSD
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, iMPACT
_io = [
("user_led", 0, Pins("D17"), IOStandard("LVCMOS25")),
("user_led", 1, Pins("AB4"), IOStandard("LVCMOS25")),
("user_led", 2, Pins("D21"), IOStandard("LVCMOS25")),
("user_led", 3, Pins("W15"), IOStandard("LVCMOS25")),
("user_btn", 0, Pins("F3"), IOStandard("LVCMOS25")),
("user_btn", 1, Pins("G6"), IOStandard("LVCMOS25")),
("user_btn", 2, Pins("F5"), IOStandard("LVCMOS25")),
("user_btn", 3, Pins("C1"), IOStandard("LVCMOS25")),
("cpu_reset", 0, Pins("H8"), IOStandard("LVCMOS25")),
("serial", 0,
Subsignal("cts", Pins("F19")),
Subsignal("rts", Pins("F18")),
Subsignal("tx", Pins("B21")),
Subsignal("rx", Pins("H17")),
IOStandard("LVCMOS25")
),
("clk200", 0,
Subsignal("p", Pins("K21")),
Subsignal("n", Pins("K22")),
IOStandard("LVDS_25")
),
("eth_clocks", 0,
# Subsignal("tx", Pins("L20")), # Comment to force GMII 1G only mode
Subsignal("gtx", Pins("AB7")),
Subsignal("rx", Pins("P20")),
IOStandard("LVCMOS25")
),
("eth", 0,
Subsignal("rst_n", Pins("J22")),
Subsignal("int_n", Pins("J20")),
Subsignal("mdio", Pins("V20")),
Subsignal("mdc", Pins("R19")),
Subsignal("rx_dv", Pins("T22")),
Subsignal("rx_er", Pins("U20")),
Subsignal("rx_data", Pins("P19 Y22 Y21 W22 W20 V22 V21 U22")),
Subsignal("tx_en", Pins("T8")),
Subsignal("tx_er", Pins("U8")),
Subsignal("tx_data", Pins("U10 T10 AB8 AA8 AB9 Y9 Y12 W12")),
Subsignal("col", Pins("M16")),
Subsignal("crs", Pins("N15")),
IOStandard("LVCMOS25")
),
]
_connectors = [
("LPC", {
"DP0_C2M_P": "B16",
"DP0_C2M_N": "A16",
"DP0_M2C_P": "D15",
"DP0_M2C_N": "C15",
"LA06_P": "D4",
"LA06_N": "D5",
"LA10_P": "H10",
"LA10_N": "H11",
"LA14_P": "C17",
"LA14_N": "A17",
"LA18_CC_P": "T12",
"LA18_CC_N": "U12",
"LA27_P": "AA10",
"LA27_N": "AB10",
"IIC_SCL_MAIN": "T21",
"IIC_SDA_MAIN": "R22",
"CLK1_M2C_P": "E16",
"CLK1_M2C_N": "F16",
"LA00_CC_P": "G9",
"LA00_CC_N": "F10",
"LA03_P": "B18",
"LA03_N": "A18",
"LA08_P": "B20",
"LA08_N": "A20",
"LA12_P": "H13",
"LA12_N": "G13",
"LA16_P": "C5",
"LA16_N": "A5",
"GBTCLK0_M2C_P": "E12",
"GBTCLK0_M2C_N": "F12",
"LA01_CC_P": "F14",
"LA01_CC_N": "F15",
"LA05_P": "C4",
"LA05_N": "A4",
"LA09_P": "F7",
"LA09_N": "F8",
"LA13_P": "G16",
"LA13_N": "F17",
"LA17_CC_P": "Y11",
"LA17_CC_N": "AB11",
"LA23_P": "U9",
"LA23_N": "V9",
"LA26_P": "U14",
"LA26_N": "U13",
"PRSNT_M2C_L": "Y16",
"CLK0_M2C_P": "H12",
"CLK0_M2C_N": "G11",
"LA02_P": "G8",
"LA02_N": "F9",
"LA04_P": "C19",
"LA04_N": "A19",
"LA07_P": "B2",
"LA07_N": "A2",
"LA11_P": "H14",
"LA11_N": "G15",
"LA15_P": "D18",
"LA20_P": "R9",
"LA20_N": "R8",
"LA22_P": "V7",
"LA22_N": "W8",
"LA25_P": "W14",
"LA25_N": "Y14",
"LA29_P": "T15",
"LA29_N": "U15",
"LA31_P": "U16",
"LA31_N": "V15",
"LA33_P": "Y17",
"LA33_N": "AB17",
"LA32_N": "Y18",
"LA15_N": "D19",
"LA19_P": "R11",
"LA19_N": "T11",
"LA21_P": "V11",
"LA21_N": "W11",
"LA24_P": "AA14",
"LA24_N": "AB14",
"LA28_P": "AA16",
"LA28_N": "AB16",
"LA30_P": "Y15",
"LA30_N": "AB15",
"LA32_P": "W17"
}),
("SMA_GPIO", {
"P": "B3",
"N": "A3"
}),
("SMA_USER_CLK", {
"P": "M20",
"N": "M19"
}),
("SMA_MGT_CLK", {
"P": "C11",
"N": "D11"
}),
]
class Platform(XilinxPlatform):
default_clk_name = "clk200"
default_clk_period = 5.0
def __init__(self):
XilinxPlatform.__init__(self, "xc6slx45t-fgg484-3", _io, _connectors, toolchain="ise")
def create_programmer(self):
return iMPACT()

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from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
from litex.build.lattice.programmer import TinyProgProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
("user_led", 0, Pins("B3"), IOStandard("LVCMOS33")),
("usb", 0,
Subsignal("d_p", Pins("B4")),
Subsignal("d_n", Pins("A4")),
Subsignal("pullup", Pins("A3")),
IOStandard("LVCMOS33")
),
("spiflash", 0,
Subsignal("cs_n", Pins("F7"), IOStandard("LVCMOS33")),
Subsignal("clk", Pins("G7"), IOStandard("LVCMOS33")),
Subsignal("mosi", Pins("G6"), IOStandard("LVCMOS33")),
Subsignal("miso", Pins("H7"), IOStandard("LVCMOS33")),
Subsignal("wp", Pins("H4"), IOStandard("LVCMOS33")),
Subsignal("hold", Pins("J8"), IOStandard("LVCMOS33"))
),
("spiflash4x", 0,
Subsignal("cs_n", Pins("F7"), IOStandard("LVCMOS33")),
Subsignal("clk", Pins("G7"), IOStandard("LVCMOS33")),
Subsignal("dq", Pins("G6 H7 H4 J8"), IOStandard("LVCMOS33"))
),
("clk16", 0, Pins("B2"), IOStandard("LVCMOS33"))
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
# A2-H2, Pins 1-13
# H9-A6, Pins 14-24
# G1-J2, Pins 25-31
("GPIO", "A2 A1 B1 C2 C1 D2 D1 E2 E1 G2 H1 J1 H2 H9 D9 D8 C9 A9 B8 A8 B7 A7 B6 A6"),
("EXTRA", "G1 J3 J4 G9 J9 E8 J2")
]
# Default peripherals
serial = [
("serial", 0,
Subsignal("tx", Pins("GPIO:0")),
Subsignal("rx", Pins("GPIO:1")),
IOStandard("LVCMOS33")
)
]
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticePlatform):
default_clk_name = "clk16"
default_clk_period = 62.5
def __init__(self):
LatticePlatform.__init__(self, "ice40-lp8k-cm81", _io, _connectors, toolchain="icestorm")
def create_programmer(self):
return TinyProgProgrammer()

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# This file is Copyright (c) 2018 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
# IOs ----------------------------------------------------------------------------------------------
_io = [
("clk25", 0, Pins("G2"), IOStandard("LVCMOS33")),
("rst", 0, Pins("R1"), IOStandard("LVCMOS33")),
("user_led", 0, Pins("B2"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("C2"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("C1"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("D2"), IOStandard("LVCMOS33")),
("user_led", 0, Pins("D1"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("E2"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("E1"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("H3"), IOStandard("LVCMOS33")),
("serial", 0,
Subsignal("tx", Pins("L4"), IOStandard("LVCMOS33")),
Subsignal("rx", Pins("M1"), IOStandard("LVCMOS33"))
),
("sdram_clock", 0, Pins("F19"), IOStandard("LVCMOS33")),
("sdram", 0,
Subsignal("a", Pins("M20 M19 L20 L19 K20 K19 K18 J20 J19 H20 N19 G20 G19")),
Subsignal("dq", Pins("J16 L18 M18 N18 P18 T18 T17 U20 E19 D20 D19 C20 E18 F18 J18 J17")),
Subsignal("we_n", Pins("T20")),
Subsignal("ras_n", Pins("R20")),
Subsignal("cas_n", Pins("T19")),
Subsignal("cs_n", Pins("P20")),
Subsignal("cke", Pins("F20")),
Subsignal("ba", Pins("P19 N20")),
Subsignal("dm", Pins("U19 E20")),
IOStandard("LVCMOS33"), Misc("SLEWRATE=FAST")
),
("wifi_gpio0", 0, Pins("L2"), IOStandard("LVCMOS33")),
("ext0p", 0, Pins("B11"), IOStandard("LVCMOS33")),
("ext1p", 0, Pins("A10"), IOStandard("LVCMOS33")),
("gpio", 0,
Subsignal("p", Pins("B11")),
Subsignal("n", Pins("C11")),
IOStandard("LVCMOS33")
),
("gpio", 1,
Subsignal("p", Pins("A10")),
Subsignal("n", Pins("A11")),
IOStandard("LVCMOS33")
),
("gpio", 2,
Subsignal("p", Pins("A9")),
Subsignal("n", Pins("B10")),
IOStandard("LVCMOS33")
),
("gpio", 3,
Subsignal("p", Pins("B9")),
Subsignal("n", Pins("C10")),
IOStandard("LVCMOS33")
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticePlatform):
default_clk_name = "clk25"
default_clk_period = 40
def __init__(self, device="LFE5U-45F", **kwargs):
LatticePlatform.__init__(self, device + "-6BG381C", _io, **kwargs)

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# This file is Copyright (c) 2013 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
from litex.build.lattice.programmer import LatticeProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
("clk100", 0, Pins("L5"), IOStandard("LVDS25")),
("rst_n", 0, Pins("A21"), IOStandard("LVCMOS33")),
("user_led", 0, Pins("Y20"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("AA21"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("U18"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("U19"), IOStandard("LVCMOS33")),
("user_led", 4, Pins("W19"), IOStandard("LVCMOS33")),
("user_led", 5, Pins("V19"), IOStandard("LVCMOS33")),
("user_led", 6, Pins("AB20"), IOStandard("LVCMOS33")),
("user_led", 7, Pins("AA20"), IOStandard("LVCMOS33")),
("user_dip_btn", 0, Pins("J7"), IOStandard("LVCMOS15")),
("user_dip_btn", 1, Pins("J6"), IOStandard("LVCMOS15")),
("user_dip_btn", 2, Pins("H2"), IOStandard("LVCMOS15")),
("user_dip_btn", 3, Pins("H3"), IOStandard("LVCMOS15")),
("user_dip_btn", 4, Pins("J3"), IOStandard("LVCMOS15")),
("user_dip_btn", 5, Pins("K3"), IOStandard("LVCMOS15")),
("user_dip_btn", 6, Pins("J2"), IOStandard("LVCMOS15")),
("user_dip_btn", 7, Pins("J1"), IOStandard("LVCMOS15")),
("serial", 0,
Subsignal("tx", Pins("B11"), IOStandard("LVCMOS33")), # X4 IO0
Subsignal("rx", Pins("B12"), IOStandard("LVCMOS33")), # X4 IO1
),
("eth_clocks", 0,
Subsignal("tx", Pins("C12")),
Subsignal("gtx", Pins("M2")),
Subsignal("rx", Pins("L4")),
IOStandard("LVCMOS33")
),
("eth", 0,
Subsignal("rst_n", Pins("L3")),
Subsignal("mdio", Pins("L2")),
Subsignal("mdc", Pins("V4")),
Subsignal("dv", Pins("M1")),
Subsignal("rx_er", Pins("M4")),
Subsignal("rx_data", Pins("M5 N1 N6 P6 T2 R2 P5 P3")),
Subsignal("tx_en", Pins("V3")),
Subsignal("tx_data", Pins("V1 U1 R3 P1 N5 N3 N4 N2")),
Subsignal("col", Pins("R1")),
Subsignal("crs", Pins("P4")),
IOStandard("LVCMOS33")
),
("eth_clocks", 1,
Subsignal("tx", Pins("M21")),
Subsignal("gtx", Pins("M19")),
Subsignal("rx", Pins("N19")),
IOStandard("LVCMOS33")
),
("eth", 1,
Subsignal("rst_n", Pins("R21")),
Subsignal("mdio", Pins("U16")),
Subsignal("mdc", Pins("Y18")),
Subsignal("dv", Pins("U15")),
Subsignal("rx_er", Pins("V20")),
Subsignal("rx_data", Pins("AB17 AA17 R19 V21 T17 R18 W21 Y21")),
Subsignal("tx_en", Pins("V22")),
Subsignal("tx_data", Pins("W22 R16 P17 Y22 T21 U22 P20 U20")),
Subsignal("col", Pins("N18")),
Subsignal("crs", Pins("P19")),
IOStandard("LVCMOS33")
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticePlatform):
default_clk_name = "clk100"
default_clk_period = 10
def __init__(self):
LatticePlatform.__init__(self, "LFE3-35EA-6FN484C", _io)
def do_finalize(self, fragment):
LatticePlatform.do_finalize(self, fragment)
try:
self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 1e9/125e6)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("eth_clocks", 1).rx, 1e9/125e6)
except ConstraintError:
pass
def create_programmer(self):
_xcf_template = """
<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
<ispXCF version="3.4.1">
<Comment></Comment>
<Chain>
<Comm>JTAG</Comm>
<Device>
<SelectedProg value="TRUE"/>
<Pos>1</Pos>
<Vendor>Lattice</Vendor>
<Family>LatticeECP3</Family>
<Name>LFE3-35EA</Name>
<File>{bitstream_file}</File>
<Operation>Fast Program</Operation>
</Device>
</Chain>
<ProjectOptions>
<Program>SEQUENTIAL</Program>
<Process>ENTIRED CHAIN</Process>
<OperationOverride>No Override</OperationOverride>
<StartTAP>TLR</StartTAP>
<EndTAP>TLR</EndTAP>
<VerifyUsercode value="FALSE"/>
</ProjectOptions>
<CableOptions>
<CableName>USB2</CableName>
<PortAdd>FTUSB-0</PortAdd>
<USBID>Dual RS232-HS A Location 0000 Serial A</USBID>
<JTAGPinSetting>
TRST ABSENT;
ISPEN ABSENT;
</JTAGPinSetting>
</CableOptions>
</ispXCF>
"""
return LatticeProgrammer(_xcf_template)

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litex_boards/official/platforms/versa_ecp5.py Normal file
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# This file is Copyright (c) 2017 Serge 'q3k' Bazanski <serge@bazanski.pl>
# License: BSD
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
from litex.build.lattice.programmer import LatticeProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
("clk100", 0, Pins("P3"), IOStandard("LVDS")),
("rst_n", 0, Pins("T1"), IOStandard("LVCMOS33")),
("user_led", 0, Pins("E16"), IOStandard("LVCMOS25")),
("user_led", 1, Pins("D17"), IOStandard("LVCMOS25")),
("user_led", 2, Pins("D18"), IOStandard("LVCMOS25")),
("user_led", 3, Pins("E18"), IOStandard("LVCMOS25")),
("user_led", 4, Pins("F17"), IOStandard("LVCMOS25")),
("user_led", 5, Pins("F18"), IOStandard("LVCMOS25")),
("user_led", 6, Pins("E17"), IOStandard("LVCMOS25")),
("user_led", 7, Pins("F16"), IOStandard("LVCMOS25")),
("user_dip_btn", 0, Pins("H2"), IOStandard("LVCMOS15")),
("user_dip_btn", 1, Pins("K3"), IOStandard("LVCMOS15")),
("user_dip_btn", 2, Pins("G3"), IOStandard("LVCMOS15")),
("user_dip_btn", 3, Pins("F2"), IOStandard("LVCMOS15")),
("user_dip_btn", 4, Pins("J18"), IOStandard("LVCMOS25")),
("user_dip_btn", 5, Pins("K18"), IOStandard("LVCMOS25")),
("user_dip_btn", 6, Pins("K19"), IOStandard("LVCMOS25")),
("user_dip_btn", 7, Pins("K20"), IOStandard("LVCMOS25")),
("serial", 0,
Subsignal("rx", Pins("C11"), IOStandard("LVCMOS33")),
Subsignal("tx", Pins("A11"), IOStandard("LVCMOS33")),
),
("ddram", 0,
Subsignal("a", Pins(
"P2 C4 E5 F5 B3 F4 B5 E4",
"C5 E3 D5 B4 C3"),
IOStandard("SSTL135_I")),
Subsignal("ba", Pins("P5 N3 M3"), IOStandard("SSTL135_I")),
Subsignal("ras_n", Pins("P1"), IOStandard("SSTL135_I")),
Subsignal("cas_n", Pins("L1"), IOStandard("SSTL135_I")),
Subsignal("we_n", Pins("M1"), IOStandard("SSTL135_I")),
Subsignal("cs_n", Pins("K1"), IOStandard("SSTL135_I")),
Subsignal("dm", Pins("J4 H5"), IOStandard("SSTL135_I")),
Subsignal("dq", Pins(
"L5 F1 K4 G1 L4 H1 G2 J3",
"D1 C1 E2 C2 F3 A2 E1 B1"),
IOStandard("SSTL135_I"),
Misc("TERMINATION=75")),
Subsignal("dqs_p", Pins("K2 H4"), IOStandard("SSTL135D_I"), Misc("TERMINATION=OFF"), Misc("DIFFRESISTOR=100")),
Subsignal("clk_p", Pins("M4"), IOStandard("SSTL135D_I")),
Subsignal("cke", Pins("N2"), IOStandard("SSTL135_I")),
Subsignal("odt", Pins("L2"), IOStandard("SSTL135_I")),
Subsignal("reset_n", Pins("N4"), IOStandard("SSTL135_I")),
Misc("SLEWRATE=FAST"),
),
("eth_clocks", 0,
Subsignal("tx", Pins("P19")),
Subsignal("rx", Pins("L20")),
IOStandard("LVCMOS25")
),
("eth", 0,
Subsignal("rst_n", Pins("U17")),
Subsignal("mdio", Pins("U18")),
Subsignal("mdc", Pins("T18")),
Subsignal("rx_ctl", Pins("U19")),
Subsignal("rx_data", Pins("T20 U20 T19 R18")),
Subsignal("tx_ctl", Pins("R20")),
Subsignal("tx_data", Pins("N19 N20 P18 P20")),
IOStandard("LVCMOS25")
),
("eth_clocks", 1,
Subsignal("tx", Pins("C20")),
Subsignal("rx", Pins("J19")),
IOStandard("LVCMOS25")
),
("eth", 1,
Subsignal("rst_n", Pins("F20")),
Subsignal("mdio", Pins("H20")),
Subsignal("mdc", Pins("G19")),
Subsignal("rx_ctl", Pins("F19")),
Subsignal("rx_data", Pins("G18 G16 H18 H17")),
Subsignal("tx_ctl", Pins("E19")),
Subsignal("tx_data", Pins("J17 J16 D19 D20")),
IOStandard("LVCMOS25")
),
("ext_clk", 0,
Subsignal("p", Pins("A4")),
Subsignal("n", Pins("A5")),
IOStandard("LVDS")
),
("pcie_x1", 0,
Subsignal("clk_p", Pins("Y11")),
Subsignal("clk_n", Pins("Y12")),
Subsignal("rx_p", Pins("Y5")),
Subsignal("rx_n", Pins("Y6")),
Subsignal("tx_p", Pins("W4")),
Subsignal("tx_n", Pins("W5")),
Subsignal("perst", Pins("A6"), IOStandard("LVCMOS33")),
),
]
_ecp5_soc_hat_io = [
("sdram_clock", 0, Pins("E14"), IOStandard("LVCMOS33")),
("sdram", 0,
Subsignal("a", Pins(
"C6 E15 A16 B16 D15 C15 B15 E12",
"D12 B10 C7 A9 C10")),
Subsignal("dq", Pins(
"B19 B12 B9 E6 D6 E7 D7 B11",
"C14 A14 E13 D13 C13 B13 A13 A12")),
Subsignal("we_n", Pins("E9")),
Subsignal("ras_n", Pins("B8")),
Subsignal("cas_n", Pins("D9")),
Subsignal("cs_n", Pins("C8")),
Subsignal("cke", Pins("D11")),
Subsignal("ba", Pins("D8 E8")),
Subsignal("dm", Pins("B6 D14")),
IOStandard("LVCMOS33"), Misc("SLEWRATE=FAST")
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
("X3",
"None", # (no pin 0)
"None", # 1 GND
"None", # 2 N/C
"None", # 3 +2V5
"B19", # 4 EXPCON_IO29
"B12", # 5 EXPCON_IO30
"B9", # 6 EXPCON_IO31
"E6", # 7 EXPCON_IO32
"D6", # 8 EXPCON_IO33
"E7", # 9 EXPCON_IO34
"D7", # 10 EXPCON_IO35
"B11", # 11 EXPCON_IO36
"B6", # 12 EXPCON_IO37
"E9", # 13 EXPCON_IO38
"D9", # 14 EXPCON_IO39
"B8", # 15 EXPCON_IO40
"C8", # 16 EXPCON_IO41
"D8", # 17 EXPCON_IO42
"E8", # 18 EXPCON_IO43
"C7", # 19 EXPCON_IO44
"C6", # 20 EXPCON_IO45
"None", # 21 +5V
"None", # 22 GND
"None", # 23 +2V5
"None", # 24 GND
"None", # 25 +3V3
"None", # 26 GND
"None", # 27 +3V3
"None", # 28 GND
"None", # 29 EXPCON_OSC
"None", # 30 GND
"None", # 31 EXPCON_CLKIN
"None", # 32 GND
"None", # 33 EXPCON_CLKOUT
"None", # 34 GND
"None", # 35 +3V3
"None", # 36 GND
"None", # 37 +3V3
"None", # 38 GND
"None", # 39 +3V3
"None", # 40 GND
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticePlatform):
default_clk_name = "clk100"
default_clk_period = 10
def __init__(self, **kwargs):
LatticePlatform.__init__(self, "LFE5UM5G-45F-8BG381C", _io, _connectors, **kwargs)
def do_finalize(self, fragment):
try:
self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 1e9/125e6)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("eth_clocks", 1).rx, 1e9/125e6)
except ConstraintError:
pass
def create_programmer(self, with_ispclock=True):
_xcf_ispclock = """
<Device>
<SelectedProg value="FALSE"/>
<Pos>2</Pos>
<Vendor>Lattice</Vendor>
<Family>ispCLOCK</Family>
<Name>ispPAC-CLK5406D</Name>
<IDCode>0x00191043</IDCode>
<Operation>Erase,Program,Verify</Operation>
<Bypass>
<InstrLen>8</InstrLen>
<InstrVal>11111111</InstrVal>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
</Device>
"""
_xcf_template = """
<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
<ispXCF version="3.4.1">
<Comment></Comment>
<Chain>
<Comm>JTAG</Comm>
<Device>
<SelectedProg value="TRUE"/>
<Pos>1</Pos>
<Vendor>Lattice</Vendor>
<Family>ECP5UM5G</Family>
<Name>LFE5UM5G-45F</Name>
<IDCode>0x81112043</IDCode>
<File>{{bitstream_file}}</File>
<Operation>Fast Program</Operation>
</Device>{ispclock}
</Chain>
<ProjectOptions>
<Program>SEQUENTIAL</Program>
<Process>ENTIRED CHAIN</Process>
<OperationOverride>No Override</OperationOverride>
<StartTAP>TLR</StartTAP>
<EndTAP>TLR</EndTAP>
<VerifyUsercode value="FALSE"/>
</ProjectOptions>
<CableOptions>
<CableName>USB2</CableName>
<PortAdd>FTUSB-0</PortAdd>
<USBID>LATTICE ECP5_5G VERSA BOARD A Location 0000 Serial Lattice ECP5_5G VERSA Board A</USBID>
</CableOptions>
</ispXCF>
""".format(ispclock=_xcf_ispclock if with_ispclock else "")
return LatticeProgrammer(_xcf_template)

0
litex_boards/official/targets/__init__.py Normal file
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litex_boards/official/targets/ac701.py Executable file
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#!/usr/bin/env python3
import argparse
from migen import *
from litex_boards.official.platforms import ac701
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import mem_decoder
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litedram.modules import MT8JTF12864
from litedram.phy import s7ddrphy
from liteeth.phy.a7_gtp import QPLLSettings, QPLL
from liteeth.phy.a7_1000basex import A7_1000BASEX
from liteeth.phy.s7rgmii import LiteEthPHYRGMII
from liteeth.core.mac import LiteEthMAC
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain()
# # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys4x.clk.attr.add("keep")
self.cd_sys4x_dqs.clk.attr.add("keep")
self.submodules.pll = pll = S7PLL(speedgrade=-1)
self.comb += pll.reset.eq(~platform.request("cpu_reset"))
pll.register_clkin(platform.request("clk200"), 200e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_clk200, 200e6)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(100e6), **kwargs):
platform = ac701.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform, sys_clk_freq)
# sdram
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = MT8JTF12864(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
# EthernetSoC --------------------------------------------------------------------------------------
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
}
mem_map.update(BaseSoC.mem_map)
def __init__(self, phy="rgmii", **kwargs):
assert phy in ["rgmii", "1000basex"]
BaseSoC.__init__(self, **kwargs)
if phy == "rgmii":
self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
self.platform.request("eth"))
self.add_csr("ethphy")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
if phy == "1000basex":
self.comb += self.platform.request("sfp_mgt_clk_sel0", 0).eq(0)
self.comb += self.platform.request("sfp_mgt_clk_sel1", 0).eq(0)
self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(0)
qpll_settings = QPLLSettings(
refclksel=0b001,
fbdiv=4,
fbdiv_45=5,
refclk_div=1)
refclk125 = self.platform.request("gtp_refclk")
refclk125_se = Signal()
self.specials += \
Instance("IBUFDS_GTE2",
i_CEB=0,
i_I=refclk125.p,
i_IB=refclk125.n,
o_O=refclk125_se)
qpll = QPLL(refclk125_se, qpll_settings)
self.submodules += qpll
self.submodules.ethphy = A7_1000BASEX(qpll.channels[0], self.platform.request("sfp", 0), self.clk_freq)
self.platform.add_period_constraint(self.ethphy.txoutclk, 1e9/62.5e6)
self.platform.add_period_constraint(self.ethphy.rxoutclk, 1e9/62.5e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.ethphy.txoutclk,
self.ethphy.rxoutclk)
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on AC701")
builder_args(parser)
soc_sdram_args(parser)
parser.add_argument("--with-ethernet", action="store_true",
help="enable Ethernet support")
parser.add_argument("--ethernet-phy", default="rgmii",
help="select Ethernet PHY (rgmii or 1000basex)")
args = parser.parse_args()
if args.with_ethernet:
soc = EthernetSoC(args.ethernet_phy, **soc_sdram_argdict(args))
else:
soc = BaseSoC(**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()
if __name__ == "__main__":
main()

117
litex_boards/official/targets/arty.py Executable file
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#!/usr/bin/env python3
import argparse
from migen import *
from litex_boards.official.platforms import arty
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import mem_decoder
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litedram.modules import MT41K128M16
from litedram.phy import s7ddrphy
from liteeth.phy.mii import LiteEthPHYMII
from liteeth.core.mac import LiteEthMAC
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain()
self.clock_domains.cd_eth = ClockDomain()
# # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys4x.clk.attr.add("keep")
self.cd_sys4x_dqs.clk.attr.add("keep")
self.submodules.pll = pll = S7PLL(speedgrade=-1)
self.comb += pll.reset.eq(~platform.request("cpu_reset"))
pll.register_clkin(platform.request("clk100"), 100e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_clk200, 200e6)
pll.create_clkout(self.cd_eth, 25e6)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
self.comb += platform.request("eth_ref_clk").eq(self.cd_eth.clk)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(100e6), **kwargs):
platform = arty.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform, sys_clk_freq)
# sdram
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = MT41K128M16(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
# EthernetSoC --------------------------------------------------------------------------------------
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
}
mem_map.update(BaseSoC.mem_map)
def __init__(self, **kwargs):
BaseSoC.__init__(self, **kwargs)
self.submodules.ethphy = LiteEthPHYMII(self.platform.request("eth_clocks"),
self.platform.request("eth"))
self.add_csr("ethphy")
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Arty")
builder_args(parser)
soc_sdram_args(parser)
parser.add_argument("--with-ethernet", action="store_true",
help="enable Ethernet support")
args = parser.parse_args()
cls = EthernetSoC if args.with_ethernet else BaseSoC
soc = cls(**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()
if __name__ == "__main__":
main()

95
litex_boards/official/targets/de0nano.py Executable file
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#!/usr/bin/env python3
import argparse
from migen import *
from litex_boards.official.platforms import de0nano
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litedram.modules import IS42S16160
from litedram.phy import GENSDRPHY
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
# # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys_ps.clk.attr.add("keep")
self.cd_por.clk.attr.add("keep")
# power on rst
rst_n = Signal()
self.sync.por += rst_n.eq(1)
self.comb += [
self.cd_por.clk.eq(self.cd_sys.clk),
self.cd_sys.rst.eq(~rst_n),
self.cd_sys_ps.rst.eq(~rst_n)
]
# sys clk / sdram clk
clk50 = platform.request("clk50")
self.comb += self.cd_sys.clk.eq(clk50)
self.specials += \
Instance("ALTPLL",
p_BANDWIDTH_TYPE="AUTO",
p_CLK0_DIVIDE_BY=1,
p_CLK0_DUTY_CYCLE=50,
p_CLK0_MULTIPLY_BY=1,
p_CLK0_PHASE_SHIFT="-3000",
p_COMPENSATE_CLOCK="CLK0",
p_INCLK0_INPUT_FREQUENCY=20000,
p_OPERATION_MODE="ZERO_DELAY_BUFFER",
i_INCLK=clk50,
o_CLK=self.cd_sys_ps.clk,
i_ARESET=~rst_n,
i_CLKENA=0x3f,
i_EXTCLKENA=0xf,
i_FBIN=1,
i_PFDENA=1,
i_PLLENA=1,
)
self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(50e6), **kwargs):
assert sys_clk_freq == int(50e6)
platform = de0nano.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform)
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = IS42S16160(self.clk_freq, "1:1")
self.register_sdram(self.sdrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on DE0 Nano")
builder_args(parser)
soc_sdram_args(parser)
args = parser.parse_args()
soc = BaseSoC(**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()
if __name__ == "__main__":
main()

96
litex_boards/official/targets/de10lite.py Executable file
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#!/usr/bin/env python3
import argparse
from migen import *
from litex_boards.official.platforms import de10lite
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litedram.modules import IS42S16320
from litedram.phy import GENSDRPHY
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
# # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys_ps.clk.attr.add("keep")
self.cd_por.clk.attr.add("keep")
# power on rst
rst_n = Signal()
self.sync.por += rst_n.eq(1)
self.comb += [
self.cd_por.clk.eq(self.cd_sys.clk),
self.cd_sys.rst.eq(~rst_n),
self.cd_sys_ps.rst.eq(~rst_n)
]
# sys clk / sdram clk
clk50 = platform.request("clk50")
self.comb += self.cd_sys.clk.eq(clk50)
self.specials += \
Instance("ALTPLL",
p_BANDWIDTH_TYPE="AUTO",
p_CLK0_DIVIDE_BY=1,
p_CLK0_DUTY_CYCLE=50,
p_CLK0_MULTIPLY_BY=1,
p_CLK0_PHASE_SHIFT="-10000",
p_COMPENSATE_CLOCK="CLK0",
p_INCLK0_INPUT_FREQUENCY=20000,
p_INTENDED_DEVICE_FAMILY="MAX 10",
p_LPM_TYPE = "altpll",
p_OPERATION_MODE = "NORMAL",
i_INCLK=clk50,
o_CLK=self.cd_sys_ps.clk,
i_ARESET=~rst_n,
i_CLKENA=0x3f,
i_EXTCLKENA=0xf,
i_FBIN=1,
i_PFDENA=1,
i_PLLENA=1,
)
self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(50e6), **kwargs):
assert sys_clk_freq == int(50e6)
platform = de10lite.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform)
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = IS42S16320(self.clk_freq, "1:1")
self.register_sdram(self.sdrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on DE10 Lite")
builder_args(parser)
soc_sdram_args(parser)
args = parser.parse_args()
soc = BaseSoC(**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()
if __name__ == "__main__":
main()

103
litex_boards/official/targets/de1soc.py Executable file
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#!/usr/bin/env python3
#
# SPDX-License-Identifier: BSD-2-Clause
#
# Copyright (C) 2019 Antony Pavlov <antonynpavlov@gmail.com>
#
# based on litex/boards/platforms/de0nano.py
#
import argparse
from migen import *
from litex_boards.official.platforms import de1soc
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litedram.modules import IS42S16320
from litedram.phy import GENSDRPHY
# CRG ------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
# # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys_ps.clk.attr.add("keep")
self.cd_por.clk.attr.add("keep")
# power on rst
rst_n = Signal()
self.sync.por += rst_n.eq(1)
self.comb += [
self.cd_por.clk.eq(self.cd_sys.clk),
self.cd_sys.rst.eq(~rst_n),
self.cd_sys_ps.rst.eq(~rst_n)
]
# sys clk / sdram clk
clk50 = platform.request("clk50")
self.comb += self.cd_sys.clk.eq(clk50)
self.specials += \
Instance("ALTPLL",
p_BANDWIDTH_TYPE="AUTO",
p_CLK0_DIVIDE_BY=1,
p_CLK0_DUTY_CYCLE=50,
p_CLK0_MULTIPLY_BY=1,
p_CLK0_PHASE_SHIFT="-3000",
p_COMPENSATE_CLOCK="CLK0",
p_INCLK0_INPUT_FREQUENCY=20000,
p_OPERATION_MODE="ZERO_DELAY_BUFFER",
i_INCLK=clk50,
o_CLK=self.cd_sys_ps.clk,
i_ARESET=~rst_n,
i_CLKENA=0x3f,
i_EXTCLKENA=0xf,
i_FBIN=1,
i_PFDENA=1,
i_PLLENA=1,
)
self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
# BaseSoC --------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(50e6), **kwargs):
assert sys_clk_freq == int(50e6)
platform = de1soc.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform)
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
# ISSI IS42S16320D-7TL
sdram_module = IS42S16320(self.clk_freq, "1:1")
self.register_sdram(self.sdrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
# Build ----------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on DE1-SoC")
builder_args(parser)
soc_sdram_args(parser)
args = parser.parse_args()
soc = BaseSoC(**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()
if __name__ == "__main__":
main()

103
litex_boards/official/targets/de2_115.py Executable file
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#!/usr/bin/env python3
#
# SPDX-License-Identifier: BSD-2-Clause
#
# Copyright (C) 2019 Antony Pavlov <antonynpavlov@gmail.com>
#
# based on litex/boards/platforms/de0nano.py
#
import argparse
from migen import *
from litex_boards.official.platforms import de2_115
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litedram.modules import IS42S16320
from litedram.phy import GENSDRPHY
# CRG ------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
# # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys_ps.clk.attr.add("keep")
self.cd_por.clk.attr.add("keep")
# power on rst
rst_n = Signal()
self.sync.por += rst_n.eq(1)
self.comb += [
self.cd_por.clk.eq(self.cd_sys.clk),
self.cd_sys.rst.eq(~rst_n),
self.cd_sys_ps.rst.eq(~rst_n)
]
# sys clk / sdram clk
clk50 = platform.request("clk50")
self.comb += self.cd_sys.clk.eq(clk50)
self.specials += \
Instance("ALTPLL",
p_BANDWIDTH_TYPE="AUTO",
p_CLK0_DIVIDE_BY=1,
p_CLK0_DUTY_CYCLE=50,
p_CLK0_MULTIPLY_BY=1,
p_CLK0_PHASE_SHIFT="-3000",
p_COMPENSATE_CLOCK="CLK0",
p_INCLK0_INPUT_FREQUENCY=20000,
p_OPERATION_MODE="ZERO_DELAY_BUFFER",
i_INCLK=clk50,
o_CLK=self.cd_sys_ps.clk,
i_ARESET=~rst_n,
i_CLKENA=0x3f,
i_EXTCLKENA=0xf,
i_FBIN=1,
i_PFDENA=1,
i_PLLENA=1,
)
self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
# BaseSoC --------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(50e6), **kwargs):
assert sys_clk_freq == int(50e6)
platform = de2_115.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform)
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
# ISSI IS42S16320D-7TL
sdram_module = IS42S16320(self.clk_freq, "1:1")
self.register_sdram(self.sdrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
# Build ----------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on DE2-115")
builder_args(parser)
soc_sdram_args(parser)
args = parser.parse_args()
soc = BaseSoC(**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()
if __name__ == "__main__":
main()

109
litex_boards/official/targets/genesys2.py Executable file
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#!/usr/bin/env python3
import argparse
from migen import *
from litex_boards.official.platforms import genesys2
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import mem_decoder
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litedram.modules import MT41J256M16
from litedram.phy import s7ddrphy
from liteeth.phy.s7rgmii import LiteEthPHYRGMII
from liteeth.core.mac import LiteEthMAC
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain()
# # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys4x.clk.attr.add("keep")
self.submodules.pll = pll = S7MMCM(speedgrade=-2)
self.comb += pll.reset.eq(~platform.request("cpu_reset_n"))
pll.register_clkin(platform.request("clk200"), 200e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_clk200, 200e6)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(125e6), **kwargs):
platform = genesys2.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform, sys_clk_freq)
# sdram
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = MT41J256M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
# EthernetSoC ------------------------------------------------------------------------------------------
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
}
mem_map.update(BaseSoC.mem_map)
def __init__(self, **kwargs):
BaseSoC.__init__(self, **kwargs)
self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
self.platform.request("eth"))
self.add_csr("ethphy")
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Genesys2")
builder_args(parser)
soc_sdram_args(parser)
parser.add_argument("--with-ethernet", action="store_true",
help="enable Ethernet support")
args = parser.parse_args()
cls = EthernetSoC if args.with_ethernet else BaseSoC
soc = cls(**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()
if __name__ == "__main__":
main()

109
litex_boards/official/targets/kc705.py Executable file
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#!/usr/bin/env python3
import argparse
from migen import *
from litex_boards.official.platforms import kc705
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import mem_decoder
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litedram.modules import MT8JTF12864
from litedram.phy import s7ddrphy
from liteeth.phy import LiteEthPHY
from liteeth.core.mac import LiteEthMAC
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain()
# # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys4x.clk.attr.add("keep")
self.submodules.pll = pll = S7MMCM(speedgrade=-2)
self.comb += pll.reset.eq(platform.request("cpu_reset"))
pll.register_clkin(platform.request("clk200"), 200e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_clk200, 200e6)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(125e6), **kwargs):
platform = kc705.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform, sys_clk_freq)
# sdram
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = MT8JTF12864(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
# EthernetSoC ------------------------------------------------------------------------------------------
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
}
mem_map.update(BaseSoC.mem_map)
def __init__(self, **kwargs):
BaseSoC.__init__(self, **kwargs)
self.submodules.ethphy = LiteEthPHY(self.platform.request("eth_clocks"),
self.platform.request("eth"), clk_freq=self.clk_freq)
self.add_csr("ethphy")
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on KC705")
builder_args(parser)
soc_sdram_args(parser)
parser.add_argument("--with-ethernet", action="store_true",
help="enable Ethernet support")
args = parser.parse_args()
cls = EthernetSoC if args.with_ethernet else BaseSoC
soc = cls(**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()
if __name__ == "__main__":
main()

150
litex_boards/official/targets/kcu105.py Executable file
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#!/usr/bin/env python3
import argparse
from migen import *
from litex_boards.official.platforms import kcu105
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import mem_decoder
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litedram.modules import EDY4016A
from litedram.phy import usddrphy
from liteeth.phy.ku_1000basex import KU_1000BASEX
from liteeth.core.mac import LiteEthMAC
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain()
self.clock_domains.cd_ic = ClockDomain()
# # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys4x.clk.attr.add("keep")
self.submodules.pll = pll = USMMCM(speedgrade=-2)
self.comb += pll.reset.eq(platform.request("cpu_reset"))
self.clock_domains.cd_pll4x = ClockDomain(reset_less=True)
pll.register_clkin(platform.request("clk125"), 125e6)
pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
pll.create_clkout(self.cd_clk200, 200e6, with_reset=False)
self.specials += [
Instance("BUFGCE_DIV", name="main_bufgce_div",
p_BUFGCE_DIVIDE=4,
i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
Instance("BUFGCE", name="main_bufgce",
i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
AsyncResetSynchronizer(self.cd_clk200, ~pll.locked),
]
ic_reset_counter = Signal(max=64, reset=63)
ic_reset = Signal(reset=1)
self.sync.clk200 += \
If(ic_reset_counter != 0,
ic_reset_counter.eq(ic_reset_counter - 1)
).Else(
ic_reset.eq(0)
)
ic_rdy = Signal()
ic_rdy_counter = Signal(max=64, reset=63)
self.cd_sys.rst.reset = 1
self.comb += self.cd_ic.clk.eq(self.cd_sys.clk)
self.sync.ic += [
If(ic_rdy,
If(ic_rdy_counter != 0,
ic_rdy_counter.eq(ic_rdy_counter - 1)
).Else(
self.cd_sys.rst.eq(0)
)
)
]
self.specials += [
Instance("IDELAYCTRL", p_SIM_DEVICE="ULTRASCALE",
i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset,
o_RDY=ic_rdy),
AsyncResetSynchronizer(self.cd_ic, ic_reset)
]
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(125e6), **kwargs):
platform = kcu105.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform, sys_clk_freq)
# sdram
self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"), memtype="DDR4", sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_constant("USDDRPHY", None)
sdram_module = EDY4016A(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
# EthernetSoC ------------------------------------------------------------------------------------------
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
}
mem_map.update(BaseSoC.mem_map)
def __init__(self, **kwargs):
BaseSoC.__init__(self, **kwargs)
self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1)
self.submodules.ethphy = KU_1000BASEX(self.crg.cd_clk200.clk,
self.platform.request("sfp", 0), sys_clk_freq=self.clk_freq)
self.add_csr("ethphy")
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
self.ethphy.cd_eth_rx.clk.attr.add("keep")
self.ethphy.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.cd_eth_rx.clk, 1e9/125e6)
self.platform.add_period_constraint(self.ethphy.cd_eth_tx.clk, 1e9/125e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.ethphy.cd_eth_rx.clk,
self.ethphy.cd_eth_tx.clk)
self.platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]")
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on KCU105")
builder_args(parser)
soc_sdram_args(parser)
parser.add_argument("--with-ethernet", action="store_true",
help="enable Ethernet support")
args = parser.parse_args()
cls = EthernetSoC if args.with_ethernet else BaseSoC
soc = cls(**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()
if __name__ == "__main__":
main()

114
litex_boards/official/targets/minispartan6.py Executable file
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#!/usr/bin/env python3
import argparse
from fractions import Fraction
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.official.platforms import minispartan6
from litex.soc.cores.clock import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litedram.modules import AS4C16M16
from litedram.phy import GENSDRPHY
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, clk_freq, use_s6pll=False):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain()
# # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys_ps.clk.attr.add("keep")
if use_s6pll:
self.submodules.pll = pll = S6PLL(speedgrade=-1)
pll.register_clkin(platform.request("clk32"), 32e6)
pll.create_clkout(self.cd_sys, clk_freq)
pll.create_clkout(self.cd_sys_ps, clk_freq, phase=270)
else:
f0 = 32*1000000
clk32 = platform.request("clk32")
clk32a = Signal()
self.specials += Instance("IBUFG", i_I=clk32, o_O=clk32a)
clk32b = Signal()
self.specials += Instance("BUFIO2", p_DIVIDE=1,
p_DIVIDE_BYPASS="TRUE", p_I_INVERT="FALSE",
i_I=clk32a, o_DIVCLK=clk32b)
f = Fraction(int(clk_freq), int(f0))
n, m, p = f.denominator, f.numerator, 8
assert f0/n*m == clk_freq
pll_lckd = Signal()
pll_fb = Signal()
pll = Signal(6)
self.specials.pll = Instance("PLL_ADV", p_SIM_DEVICE="SPARTAN6",
p_BANDWIDTH="OPTIMIZED", p_COMPENSATION="INTERNAL",
p_REF_JITTER=.01, p_CLK_FEEDBACK="CLKFBOUT",
i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0,
p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=m*p//n, p_CLKFBOUT_PHASE=0.,
i_CLKIN1=clk32b, i_CLKIN2=0, i_CLKINSEL=1,
p_CLKIN1_PERIOD=1000000000/f0, p_CLKIN2_PERIOD=0.,
i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd,
o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5,
o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5,
o_CLKOUT2=pll[2], p_CLKOUT2_DUTY_CYCLE=.5,
o_CLKOUT3=pll[3], p_CLKOUT3_DUTY_CYCLE=.5,
o_CLKOUT4=pll[4], p_CLKOUT4_DUTY_CYCLE=.5,
o_CLKOUT5=pll[5], p_CLKOUT5_DUTY_CYCLE=.5,
p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=p//1,
p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=p//1,
p_CLKOUT2_PHASE=0., p_CLKOUT2_DIVIDE=p//1,
p_CLKOUT3_PHASE=0., p_CLKOUT3_DIVIDE=p//1,
p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=p//1, # sys
p_CLKOUT5_PHASE=270., p_CLKOUT5_DIVIDE=p//1, # sys_ps
)
self.specials += Instance("BUFG", i_I=pll[4], o_O=self.cd_sys.clk)
self.specials += Instance("BUFG", i_I=pll[5], o_O=self.cd_sys_ps.clk)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd)
self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE",
p_INIT=0, p_SRTYPE="SYNC",
i_D0=0, i_D1=1, i_S=0, i_R=0, i_CE=1,
i_C0=self.cd_sys.clk, i_C1=~self.cd_sys.clk,
o_Q=platform.request("sdram_clock"))
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(80e6), **kwargs):
assert sys_clk_freq == int(80e6)
platform = minispartan6.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform, sys_clk_freq)
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = AS4C16M16(sys_clk_freq, "1:1")
self.register_sdram(self.sdrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on MiniSpartan6")
builder_args(parser)
soc_sdram_args(parser)
args = parser.parse_args()
soc = BaseSoC(**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()
if __name__ == "__main__":
main()

114
litex_boards/official/targets/netv2.py Executable file
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#!/usr/bin/env python3
import argparse
from migen import *
from litex_boards.official.platforms import netv2
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import mem_decoder
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litedram.modules import MT41J128M16
from litedram.phy import s7ddrphy
from liteeth.phy.rmii import LiteEthPHYRMII
from liteeth.core.mac import LiteEthMAC
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain()
self.clock_domains.cd_eth = ClockDomain()
# # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys4x.clk.attr.add("keep")
self.cd_sys4x_dqs.clk.attr.add("keep")
self.submodules.pll = pll = S7PLL(speedgrade=-1)
pll.register_clkin(platform.request("clk50"), 50e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_clk200, 200e6)
pll.create_clkout(self.cd_eth, 50e6)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(100e6), **kwargs):
platform = netv2.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform, sys_clk_freq)
# sdram
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = MT41J128M16(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
# EthernetSoC --------------------------------------------------------------------------------------
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
}
mem_map.update(BaseSoC.mem_map)
def __init__(self, **kwargs):
BaseSoC.__init__(self, **kwargs)
self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"),
self.platform.request("eth"))
self.add_csr("ethphy")
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on NeTV2")
builder_args(parser)
soc_sdram_args(parser)
parser.add_argument("--with-ethernet", action="store_true",
help="enable Ethernet support")
args = parser.parse_args()
cls = EthernetSoC if args.with_ethernet else BaseSoC
soc = cls(**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()
if __name__ == "__main__":
main()

118
litex_boards/official/targets/nexys4ddr.py Executable file
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#!/usr/bin/env python3
import argparse
from migen import *
from litex_boards.official.platforms import nexys4ddr
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import mem_decoder
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litedram.modules import MT47H64M16
from litedram.phy import s7ddrphy
from liteeth.phy.rmii import LiteEthPHYRMII
from liteeth.core.mac import LiteEthMAC
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys2x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain()
self.clock_domains.cd_eth = ClockDomain()
# # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys2x.clk.attr.add("keep")
self.cd_sys2x_dqs.clk.attr.add("keep")
self.submodules.pll = pll = S7MMCM(speedgrade=-1)
self.comb += pll.reset.eq(~platform.request("cpu_reset"))
pll.register_clkin(platform.request("clk100"), 100e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
pll.create_clkout(self.cd_sys2x_dqs, 2*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_clk200, 200e6)
pll.create_clkout(self.cd_eth, 50e6)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(100e6), **kwargs):
platform = nexys4ddr.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform, sys_clk_freq)
# sdram
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), memtype="DDR2", nphases=2, sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = MT47H64M16(sys_clk_freq, "1:2")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
self.add_constant("MEMTEST_ADDR_SIZE", 0) # FIXME
# EthernetSoC --------------------------------------------------------------------------------------
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
}
mem_map.update(BaseSoC.mem_map)
def __init__(self, **kwargs):
BaseSoC.__init__(self, **kwargs)
self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"),
self.platform.request("eth"))
self.add_csr("ethphy")
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Nexys4DDR")
builder_args(parser)
soc_sdram_args(parser)
parser.add_argument("--sys-clk-freq", default=75e6,
help="system clock frequency (default=75MHz)")
parser.add_argument("--with-ethernet", action="store_true",
help="enable Ethernet support")
args = parser.parse_args()
cls = EthernetSoC if args.with_ethernet else BaseSoC
soc = cls(sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()
if __name__ == "__main__":
main()

113
litex_boards/official/targets/nexys_video.py Executable file
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#!/usr/bin/env python3
import argparse
from migen import *
from litex_boards.official.platforms import nexys_video
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import mem_decoder
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litedram.modules import MT41K256M16
from litedram.phy import s7ddrphy
from liteeth.phy.s7rgmii import LiteEthPHYRGMII
from liteeth.core.mac import LiteEthMAC
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain()
self.clock_domains.cd_clk100 = ClockDomain()
# # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys4x.clk.attr.add("keep")
self.cd_sys4x_dqs.clk.attr.add("keep")
self.submodules.pll = pll = S7MMCM(speedgrade=-1)
self.comb += pll.reset.eq(~platform.request("cpu_reset"))
pll.register_clkin(platform.request("clk100"), 100e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_clk200, 200e6)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(100e6), **kwargs):
platform = nexys_video.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform, sys_clk_freq)
# sdram
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = MT41K256M16(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
# EthernetSoC --------------------------------------------------------------------------------------
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
}
mem_map.update(BaseSoC.mem_map)
def __init__(self, **kwargs):
BaseSoC.__init__(self, **kwargs)
self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
self.platform.request("eth"))
self.add_csr("ethphy")
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Nexys Video")
builder_args(parser)
soc_sdram_args(parser)
parser.add_argument("--with-ethernet", action="store_true",
help="enable Ethernet support")
args = parser.parse_args()
cls = EthernetSoC if args.with_ethernet else BaseSoC
soc = cls(**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()
if __name__ == "__main__":
main()

85
litex_boards/official/targets/ulx3s.py Executable file
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#!/usr/bin/env python3
import argparse
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.official.platforms import ulx3s
from litex.soc.cores.clock import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litedram.modules import MT48LC16M16
from litedram.phy import GENSDRPHY
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
# # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys_ps.clk.attr.add("keep")
# clk / rst
clk25 = platform.request("clk25")
rst = platform.request("rst")
platform.add_period_constraint(clk25, 40.0)
# pll
self.submodules.pll = pll = ECP5PLL()
self.comb += pll.reset.eq(rst)
pll.register_clkin(clk25, 25e6)
pll.create_clkout(self.cd_sys, sys_clk_freq, phase=11)
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=20)
self.specials += AsyncResetSynchronizer(self.cd_sys, rst)
# sdram clock
self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
# Stop ESP32 from resetting FPGA
wifi_gpio0 = platform.request("wifi_gpio0")
self.comb += wifi_gpio0.eq(1)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, device="LFE5U-45F", toolchain="diamond", **kwargs):
platform = ulx3s.Platform(device=device, toolchain=toolchain)
sys_clk_freq = int(50e6)
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform, sys_clk_freq)
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = MT48LC16M16(sys_clk_freq, "1:1")
self.register_sdram(self.sdrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on ULX3S")
parser.add_argument("--gateware-toolchain", dest="toolchain", default="diamond",
help='gateware toolchain to use, diamond (default) or trellis')
parser.add_argument("--device", dest="device", default="LFE5U-45F",
help='FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F')
builder_args(parser)
soc_sdram_args(parser)
args = parser.parse_args()
soc = BaseSoC(device=args.device, toolchain=args.toolchain, **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()
if __name__ == "__main__":
main()

145
litex_boards/official/targets/versa_ecp5.py Executable file
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#!/usr/bin/env python3
import argparse
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.official.platforms import versa_ecp5
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import mem_decoder
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litedram.modules import MT41K64M16
from litedram.phy import ECP5DDRPHY
from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
from liteeth.core.mac import LiteEthMAC
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_init = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
# # #
self.cd_init.clk.attr.add("keep")
self.cd_por.clk.attr.add("keep")
self.cd_sys.clk.attr.add("keep")
self.cd_sys2x.clk.attr.add("keep")
self.cd_sys2x_i.clk.attr.add("keep")
self.stop = Signal()
# clk / rst
clk100 = platform.request("clk100")
rst_n = platform.request("rst_n")
platform.add_period_constraint(clk100, 1e9/100e6)
# power on reset
por_count = Signal(16, reset=2**16-1)
por_done = Signal()
self.comb += self.cd_por.clk.eq(ClockSignal())
self.comb += por_done.eq(por_count == 0)
self.sync.por += If(~por_done, por_count.eq(por_count - 1))
# pll
self.submodules.pll = pll = ECP5PLL()
pll.register_clkin(clk100, 100e6)
pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
pll.create_clkout(self.cd_init, 25e6)
self.specials += [
Instance("ECLKSYNCB",
i_ECLKI=self.cd_sys2x_i.clk,
i_STOP=self.stop,
o_ECLKO=self.cd_sys2x.clk),
Instance("CLKDIVF",
p_DIV="2.0",
i_ALIGNWD=0,
i_CLKI=self.cd_sys2x.clk,
i_RST=self.cd_sys2x.rst,
o_CDIVX=self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked | ~rst_n),
AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | ~rst_n)
]
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", **kwargs):
platform = versa_ecp5.Platform(toolchain=toolchain)
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
**kwargs)
# crg
crg = _CRG(platform, sys_clk_freq)
self.submodules.crg = crg
# sdram
self.submodules.ddrphy = ECP5DDRPHY(
platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_constant("ECP5DDRPHY", None)
self.comb += crg.stop.eq(self.ddrphy.init.stop)
sdram_module = MT41K64M16(sys_clk_freq, "1:2")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
# EthernetSoC --------------------------------------------------------------------------------------
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
}
mem_map.update(BaseSoC.mem_map)
def __init__(self, toolchain="diamond", **kwargs):
BaseSoC.__init__(self, toolchain=toolchain, **kwargs)
self.submodules.ethphy = LiteEthPHYRGMII(
self.platform.request("eth_clocks"),
self.platform.request("eth"))
self.add_csr("ethphy")
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Versa ECP5")
parser.add_argument("--gateware-toolchain", dest="toolchain", default="diamond",
help='gateware toolchain to use, diamond (default) or trellis')
builder_args(parser)
soc_sdram_args(parser)
parser.add_argument("--sys-clk-freq", default=75e6,
help="system clock frequency (default=75MHz)")
parser.add_argument("--with-ethernet", action="store_true",
help="enable Ethernet support")
args = parser.parse_args()
cls = EthernetSoC if args.with_ethernet else BaseSoC
soc = cls(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()
if __name__ == "__main__":
main()

34
setup.py Executable file
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#!/usr/bin/env python3
import sys
from setuptools import setup
from setuptools import find_packages
if sys.version_info[:3] < (3, 5):
raise SystemExit("You need Python 3.5+")
setup(
name="litex-boards",
description="LiteX supported boards",
long_description=open("README").read(),
author="Florent Kermarrec",
author_email="florent@enjoy-digital.fr",
url="http://enjoy-digital.fr",
download_url="https://github.com/litex-hub/litex-boards",
test_suite="test",
license="BSD",
platforms=["Any"],
keywords="HDL ASIC FPGA hardware design",
classifiers=[
"Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
"Environment :: Console",
"Development Status :: Alpha",
"Intended Audience :: Developers",
"License :: OSI Approved :: BSD License",
"Operating System :: OS Independent",
"Programming Language :: Python",
],
include_package_data=True,
)