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sipeed_tang_nano_4k: allow non-vexriscv CPUs

This commit is contained in:
Ilia Sergachev 2021-12-08 23:33:49 +01:00
parent 8ad89881c2
commit 4287ab561e
1 changed files with 3 additions and 3 deletions
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6
litex_boards/targets/sipeed_tang_nano_4k.py
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@ -72,15 +72,15 @@ class BaseSoC(SoCCore):
kwargs["integrated_rom_size"] = 0 kwargs["integrated_rom_size"] = 0
kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + 0 kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + 0
kwargs["cpu_type"] = 'vexriscv'
kwargs["cpu_variant"] = 'minimal'
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Tang Nano 4K", ident = "LiteX SoC on Tang Nano 4K",
ident_version = True, ident_version = True,
**kwargs) **kwargs)
if self.cpu_type == 'vexriscv':
assert self.cpu_variant == 'minimal', 'use --cpu-variant=minimal to fit into number of BSRAMs'
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, with_video_pll=with_video_terminal) self.submodules.crg = _CRG(platform, sys_clk_freq, with_video_pll=with_video_terminal)