add QMTech 5CEFA5 Cyclone V board support
This commit is contained in:
Hans Baier
parent
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2023 Hans Baier <hansfbaier@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.altera import AlteraPlatform
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from litex.build.altera.programmer import USBBlaster
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk
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("clk50", 0, Pins("M9"), IOStandard("3.3-V LVCMOS")),
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# Button
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("key", 0, Pins("J17"), IOStandard("3.3-V LVCMOS")),
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("key", 1, Pins("E16"), IOStandard("3.3-V LVCMOS")),
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# SPIFlash (MT25QL128ABA)
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("spiflash", 0,
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# clk
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Subsignal("cs_n", Pins("R4")),
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Subsignal("clk", Pins("V3")),
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Subsignal("mosi", Pins("AB4")),
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Subsignal("miso", Pins("AB3")),
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IOStandard("3.3-V LVCMOS"),
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),
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# SDR SDRAM
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("sdram_clock", 0, Pins("G18"), IOStandard("3.3-V LVCMOS")),
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("sdram", 0,
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Subsignal("a", Pins(
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# A0 A1 A2 A3 A4 A5 A6 A7
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"M18 M20 M16 L17 L19 L18 K16 K17",
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# A8 A9 A10 A11 A12
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"J18 J19 N19 H18 H20")),
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Subsignal("ba", Pins("P19 P18")),
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Subsignal("cs_n", Pins("P17")),
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Subsignal("cke", Pins("G17")),
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Subsignal("ras_n", Pins("P16")),
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Subsignal("cas_n", Pins("T19")),
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Subsignal("we_n", Pins("U20")),
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Subsignal("dq", Pins(
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"AA22 AB22 Y22 Y21 W22 W21 V21 U22 M21 M22 T22 R21 R22 P22 N20 N21 ",
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"K22 K21 J22 J21 H21 G22 G21 F22 E22 E20 D22 D21 C21 B22 A22 B21")),
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Subsignal("dm", Pins("U21 L22 K20 E21")),
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IOStandard("3.3-V LVCMOS")
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),
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]
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# The connectors are named after the daughterboard, not the core board
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# because on the different core boards the names vary, but on the
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# daughterboard they stay the same, which we need to connect the
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# daughterboard peripherals to the core board.
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# On this board J2 is U6 and J3 is U5
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_connectors = [
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("J2", {
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# odd row even row
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7: "AB21", 8: "AB20",
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9: "Y19", 10: "Y20",
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11: "AA20", 12: "AA19",
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13: "W19", 14: "V20",
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15: "AB18", 16: "AB17",
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17: "U17", 18: "U16",
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19: "R16", 20: "R17",
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21: "T15", 22: "R15",
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23: "R14", 24: "P14",
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25: "AA15", 26: "AB15",
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27: "T13", 28: "T12",
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29: "R11", 30: "R10",
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31: "AA13", 32: "AA14",
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33: "Y15", 34: "Y14",
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35: "AB12", 36: "AB13",
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37: "AB11", 38: "AB10",
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39: "V10", 40: "V9",
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41: "U12", 42: "U11",
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43: "R9", 44: "T10",
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45: "T8", 46: "T7",
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47: "N8", 48: "P8",
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49: "M7", 50: "M6",
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51: "N6", 52: "P6",
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53: "R5", 54: "R6",
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55: "AB8", 56: "AA8 ",
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57: "AB7", 58: "AA7",
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59: "AB5", 60: "AB6",
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}),
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("J3", {
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# odd row even row
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7: "F19", 8: "F18",
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9: "E19", 10: "D19",
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11: "C20", 12: "B20",
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13: "A20", 14: "A19",
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15: "C19", 16: "C18",
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17: "A18", 18: "A17",
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19: "B18", 20: "B17",
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21: "B16", 22: "C16",
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23: "C15", 24: "B15",
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25: "E15", 26: "F15",
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27: "A15", 28: "A14",
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29: "B13", 30: "A13",
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31: "B12", 32: "A12",
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33: "G15", 34: "F14",
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35: "H13", 36: "G13",
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37: "D12", 38: "E12",
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39: "H11", 40: "G12",
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41: "A10", 42: "A9",
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43: "J9", 44: "H9",
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45: "E9", 46: "D9",
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47: "H8", 48: "G8",
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49: "L7", 50: "K7",
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51: "J7", 52: "J8",
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53: "A8", 54: "A7",
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55: "B6", 56: "B7",
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57: "C6", 58: "D6",
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59: "A5", 60: "B5",
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})
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(AlteraPlatform):
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default_clk_name = "clk50"
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default_clk_period = 1e9/50e6
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core_resources = [
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("user_led", 0, Pins("V19"), IOStandard("3.3-V LVCMOS")),
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("user_led", 1, Pins("T20"), IOStandard("3.3-V LVCMOS")),
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("serial", 0,
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Subsignal("tx", Pins("J3:7"), IOStandard("3.3-V LVCMOS")),
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Subsignal("rx", Pins("J3:8"), IOStandard("3.3-V LVCMOS"))
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),
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]
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def __init__(self, toolchain="quartus", with_daughterboard=False):
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device = "5CEFA5F23I7"
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io = _io
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connectors = _connectors
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if with_daughterboard:
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from litex_boards.platforms.qmtech_daughterboard import QMTechDaughterboard
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daughterboard = QMTechDaughterboard(IOStandard("3.3-V LVCMOS"))
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io += daughterboard.io
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connectors += daughterboard.connectors
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else:
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io += self.core_resources
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AlteraPlatform.__init__(self, device, io, connectors, toolchain=toolchain)
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if with_daughterboard:
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# ethernet takes the config pin, so make it available
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self.add_platform_command("set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION \"USE AS REGULAR IO\"")
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# Generate PLL clock in STA
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self.toolchain.additional_sdc_commands.append("derive_pll_clocks")
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# Calculates clock uncertainties
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self.toolchain.additional_sdc_commands.append("derive_clock_uncertainty")
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def create_programmer(self):
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return USBBlaster()
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def do_finalize(self, fragment):
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AlteraPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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@ -0,0 +1,186 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2023 Hans Baier <hansfbaier@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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#
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# Note: The CPU actually runs at over 100MHz, but the SDRAM only works up to 75MHz
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from migen import *
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from litex.gen import *
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from litex.build.io import DDROutput
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from litex_boards.platforms import qmtech_5cefa5
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from litex.soc.cores.clock import CycloneVPLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import W9825G6KH6
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from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
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from litex.soc.cores.video import VideoVGAPHY
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from liteeth.phy.mii import LiteEthPHYMII
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, with_ethernet, with_vga, sdram_rate="1:1"):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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if sdram_rate == "1:2":
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self.cd_sys2x = ClockDomain()
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self.cd_sys2x_ps = ClockDomain()
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else:
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self.cd_sys_ps = ClockDomain()
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if with_ethernet:
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self.cd_eth = ClockDomain()
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if with_vga:
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self.cd_vga = ClockDomain()
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# # #
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# Clk / Rst
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clk50 = platform.request("clk50")
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# PLL
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self.pll = pll = CycloneVPLL(speedgrade="-C8")
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk50, 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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if sdram_rate == "1:2":
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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# theoretically 90 degrees, but increase to relax timing
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pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180)
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else:
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=45)
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if with_ethernet:
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pll.create_clkout(self.cd_eth, 25e6)
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if with_vga:
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pll.create_clkout(self.cd_vga, 40e6)
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# SDRAM clock
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sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
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self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=80e6, with_daughterboard=False,
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with_ethernet = False,
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with_etherbone = False,
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eth_ip = "192.168.1.50",
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eth_dynamic_ip = False,
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with_led_chaser = True,
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with_video_terminal = False,
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with_video_framebuffer = False,
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sdram_rate = "1:1",
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**kwargs):
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platform = qmtech_5cefa5.Platform(with_daughterboard=with_daughterboard)
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq,
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with_ethernet = with_ethernet or with_etherbone,
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with_vga = with_video_terminal or with_video_framebuffer,
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sdram_rate = sdram_rate
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)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on QMTECH 5CEFA5" + (" + Daughterboard" if with_daughterboard else ""),
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**kwargs)
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# SDR SDRAM --------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
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self.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = W9825G6KH6(sys_clk_freq, sdram_rate),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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self.ethphy = LiteEthPHYMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"))
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if with_ethernet:
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self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
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# Video ------------------------------------------------------------------------------------
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if with_video_terminal or with_video_framebuffer:
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self.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga")
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if with_video_terminal:
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self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
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if with_video_framebuffer:
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self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=qmtech_5cefa5.Platform, description="LiteX SoC on QMTECH 5CEFA5.")
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parser.add_target_argument("--sys-clk-freq", default=80e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
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parser.add_target_argument("--with-daughterboard", action="store_true", help="Board plugged into the QMTech daughterboard.")
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ethopts = parser.target_group.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
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parser.add_target_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
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parser.add_target_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
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sdopts = parser.target_group.add_mutually_exclusive_group()
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sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
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sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
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parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
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viopts = parser.target_group.add_mutually_exclusive_group()
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viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
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viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (VGA).")
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = args.sys_clk_freq,
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with_daughterboard = args.with_daughterboard,
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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eth_ip = args.eth_ip,
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eth_dynamic_ip = args.eth_dynamic_ip,
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with_video_terminal = args.with_video_terminal,
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with_video_framebuffer = args.with_video_framebuffer,
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with_spi_flash = args.with_spi_flash,
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sdram_rate = args.sdram_rate,
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**parser.soc_argdict
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)
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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if args.with_sdcard:
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soc.add_sdcard()
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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