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icebreaker/nexys4ddr: Use new LiteXSoC's add_video_terminal method to add the Video Terminal.

This commit is contained in:
Florent Kermarrec 2021-03-03 17:47:20 +01:00
parent 3af8ec0c8d
commit 465a95d2a6
2 changed files with 7 additions and 35 deletions
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20
litex_boards/targets/icebreaker.py
View File

@ -31,8 +31,8 @@ from litex.soc.cores.clock import iCE40PLL
from litex.soc.integration.soc_core import *
from litex.soc.integration.soc import SoCRegion
from litex.soc.integration.builder import *
from litex.soc.cores.video import VideoDVIPHY
from litex.soc.cores.led import LedChaser
from litex.soc.cores.video import *
kB = 1024
mB = 1024*kB
@ -110,21 +110,9 @@ class BaseSoC(SoCCore):
# Video Terminal ---------------------------------------------------------------------------
if with_video_terminal:
self.platform.add_extension(icebreaker.dvi_pmod)
self.submodules.vtg = vtg = VideoTimingGenerator(default_video_timings="800x600@60Hz")
self.add_csr("vtg")
#self.submodules.vgen = vgen = ColorBarsPattern()
self.submodules.vgen = vgen = VideoTerminal(hres=800, vres=600)
self.submodules.vphy = vphy = VideoDVIPHY(platform.request("dvi"), clock_domain="sys")
self.comb += [
# Connect UART to Video Terminal.
vgen.uart_sink.valid.eq(self.uart.source.valid & self.uart.source.ready),
vgen.uart_sink.data.eq(self.uart.source.data),
# Connect Video Timing Generator to Video Terminal.
vtg.source.connect(vgen.vtg_sink),
# Connect VideoTerminal to VideoDVIPHY.
vgen.source.connect(vphy.sink),
]
platform.add_extension(icebreaker.dvi_pmod)
self.submodules.videophy = VideoDVIPHY(platform.request("dvi"), clock_domain="sys")
self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="sys")
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(

22
litex_boards/targets/nexys4ddr.py
View File

@ -18,6 +18,7 @@ from litex.soc.integration.soc import SoCRegion
from litex.soc.integration.soc_core import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litex.soc.cores.video import VideoVGAPHY
from litex.soc.cores.led import LedChaser
from litedram.modules import MT47H64M16
@ -25,8 +26,6 @@ from litedram.phy import s7ddrphy
from liteeth.phy.rmii import LiteEthPHYRMII
from litex.soc.cores.video import *
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
@ -98,23 +97,8 @@ class BaseSoC(SoCCore):
# Video Terminal ---------------------------------------------------------------------------
if with_video_terminal:
self.submodules.vtg = vtg = ClockDomainsRenamer("vga")(VideoTimingGenerator(default_video_timings="800x600@60Hz"))
self.add_csr("vtg")
#self.submodules.vgen = vgen = ClockDomainsRenamer("vga")(ColorBarsPattern())
self.submodules.vgen = vgen = ClockDomainsRenamer("vga")(VideoTerminal(hres=800, vres=600))
self.submodules.vphy = vphy = VideoVGAPHY(platform.request("vga"), clock_domain="vga")
from litex.soc.interconnect import stream
self.submodules.uart_cdc = stream.ClockDomainCrossing([("data", 8)], cd_from="sys", cd_to="vga")
self.comb += [
# Connect UART to Video Terminal.
self.uart_cdc.sink.valid.eq(self.uart.source.valid & self.uart.source.ready),
self.uart_cdc.sink.data.eq(self.uart.source.data),
self.uart_cdc.source.connect(vgen.uart_sink),
# Connect Video Timing Generator to Video Terminal.
vtg.source.connect(vgen.vtg_sink),
# Connect VideoTerminal to VideoDVIPHY.
vgen.source.connect(vphy.sink),
]
self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga")
self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(