Wukong board improvements
This adds support for v2 of the board via a --board-version argument and a way to select the FPGA speed grade via a --speed-grade argument. Note that the speed grade now defaults to -1. QMTech confirmed that V1 of the board were made in two batches, one with -1 and one with -2, while V2 of the board is all -1. So -1 is the safer default. This also fixes the inversion of j10 and j11 and a typo in the pin definition of jp3 Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Benjamin Herrenschmidt
Benjamin Herrenschmidt
parent
610e82d774
commit
4a52996106
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@ -151,6 +151,8 @@ The Colorlight5A is a very nice board to start with, cheap, powerful, easy to us
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| Nexys4DDR | Xilinx Artix7 | XC7A100T | 100MHz | FTDI | 16-bit 128MB DDR2 | No | 100Mbps RMII | 16MB QSPI* | Yes |
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| Nexys Video | Xilinx Artix7 | XC7A200T | 100MHz | FTDI | 16-bit 512MB DDR3 | No | 1Gbps RMII | 32MB QSPI* | Yes |
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| QMTech XC7A35T | Xilinx Artix7 | XC7A35T | 100MHz | FTDI | 16-bit 256MB DDR3 | No | 1Gbps GMII** | 16MB QSPI | Yes**|
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| QMTech Wukong1 | Xilinx Artix7 | XC7A100T | 100MHz | FTDI | 16-bit 256MB DDR3 | No | 1Gbps GMII | 16MB QSPI | Yes**|
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| QMTech Wukong2 | Xilinx Artix7 | XC7A100T/200T | 100MHz | FTDI | 16-bit 256MB DDR3 | No | 1Gbps GMII | 16MB QSPI | Yes |
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| RZ-EasyFPGA | Intel Cyclone4 | EP4CE6 | 25MHz | IOs | 16-bit 8MB SDR | No | No | No | No |
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| SP605 | Xilinx Spartan6 | XC6SLX45T | 100MHz | FTDI | 16-bit 128MB DDR3* | Gen1 X1* | 1Gbps GMII | 8MB QSPI* | Yes* |
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| Tagus | Xilinx Artix7 | XC7A200T | 100MHz | PCIe | 16-bit 256MB DDR3 | Gen2 X1 | 1Gbps-BASE-X* | 16MB QSPI* | No |
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@ -10,17 +10,46 @@ from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk50", 0, Pins("M22"), IOStandard("LVCMOS33")),
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("cpu_reset", 0, Pins("J8"), IOStandard("LVCMOS33")),
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# IOs specific to V1 of the board
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_io_v1 = [
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# Reset (Key1 button)
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("cpu_reset", 0, Pins("J8"), IOStandard("LVCMOS33")), # key1
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#Clock
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("clk50" , 0, Pins("M22"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("J6"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("H6"), IOStandard("LVCMOS33")),
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]
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# Buttons
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("user_btn", 0, Pins("H7"), IOStandard("LVCMOS33")), # Key0
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# IOs specific to V2 of the board
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_io_v2 = [
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# Reset (Key1 button)
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("cpu_reset", 0, Pins("M6"), IOStandard("LVCMOS33")),
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# Clock
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("clk50" , 0, Pins("M21"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("V16"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("V17"), IOStandard("LVCMOS33")),
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# SD-Card
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("sdcard", 0,
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Subsignal("data", Pins("M5 M7 H6 J6")),
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Subsignal("cmd", Pins("J8")),
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Subsignal("clk", Pins("L4")),
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Subsignal("cd", Pins("N6")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS33"),
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),
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]
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# IO commons to both versions of the board
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_io_common = [
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# Key0 button (Key1 is used as cpu reset and is version specific)
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("user_btn", 0, Pins("H7"), IOStandard("LVCMOS33")),
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# Serial
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("serial", 0,
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@ -56,6 +85,8 @@ _io = [
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Subsignal("ras_n", Pins("A19"), IOStandard("SSTL135")),
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Subsignal("cas_n", Pins("B19"), IOStandard("SSTL135")),
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Subsignal("we_n", Pins("A18"), IOStandard("SSTL135")),
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# cs_n is only wired on V1 of the board but E22 is unconnected on V2
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# so leaving this here shouldn't hurt
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Subsignal("cs_n", Pins("E22"), IOStandard("SSTL135")),
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Subsignal("dm", Pins("A22 C22"), IOStandard("SSTL135")),
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Subsignal("dq", Pins(
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@ -119,8 +150,8 @@ _io = [
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("j10", "H4 F4 A4 A5 J4 G4 B4 B5"),
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("j11", "D5 G5 G7 G8 E5 E6 D6 G6"),
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("j10", "D5 G5 G7 G8 E5 E6 D6 G6"),
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("j11", "H4 F4 A4 A5 J4 G4 B4 B5"),
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("j12", "AB26 AC26 AB24 AC24 AA24 AB25 AA22 AA23",
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" Y25 AA25 W25 Y26 Y22 Y23 W21 Y21",
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" V26 W26 U25 U26 V24 W24 V23 W23",
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@ -128,7 +159,7 @@ _connectors = [
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" T19 U19"),
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("jp2", "H21 H22 K21 J21 H26 G26 G25 F25",
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"G20 G21 F23 E23 E26 D26 E25 D25"),
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("jp3", " AF7 AE7 AD8 AC8 AF9 AE9 AD12 AC10",
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("jp3", " AF7 AE7 AD8 AC8 AF9 AE9 AD10 AC10",
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"AA11 AB11 AF11 AE11 AD14 AC14 AF13 AE13",
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"AD12 AC12"),
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]
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@ -169,14 +200,20 @@ class Platform(XilinxPlatform):
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default_clk_name = "clk50"
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default_clk_period = 1e9/50e6
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def __init__(self):
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XilinxPlatform.__init__(self, "xc7a100t-2fgg676", _io, _connectors, toolchain="vivado")
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def __init__(self, board_version=1, speed_grade=-2):
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io = _io_common
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if board_version < 2:
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io.extend(_io_v1)
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else:
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io.extend(_io_v2)
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XilinxPlatform.__init__(self, "xc7a100t{}fgg676".format(speed_grade), io, _connectors, toolchain="vivado")
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix4 -size 16 "
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 16]")
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if board_version < 2:
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self.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk50_IBUF]")
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self.add_platform_command("set_property CFGBVS VCCO [current_design]")
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self.add_platform_command("set_property CONFIG_VOLTAGE 3.3 [current_design]")
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@ -31,7 +31,7 @@ from liteeth.phy import LiteEthPHYMII
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, with_video_pll=False, pix_clk=25.175e6):
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def __init__(self, platform, speed_grade, sys_clk_freq, with_video_pll=False, pix_clk=25.175e6):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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@ -46,7 +46,7 @@ class _CRG(Module):
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plls_reset = platform.request("cpu_reset")
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plls_clk50 = platform.request("clk50")
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self.submodules.pll = pll = S7MMCM(speedgrade=-2)
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self.submodules.pll = pll = S7MMCM(speedgrade=speed_grade)
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self.comb += pll.reset.eq(~plls_reset | self.rst)
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pll.register_clkin(plls_clk50, 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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@ -55,7 +55,7 @@ class _CRG(Module):
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#pll.create_clkout(self.cd_idelay, 200e6)
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# idelay PLL
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self.submodules.pll_idelay = pll_idelay = S7PLL(speedgrade=-2)
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self.submodules.pll_idelay = pll_idelay = S7PLL(speedgrade=speed_grade)
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self.comb += pll_idelay.reset.eq(~plls_reset | self.rst)
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pll_idelay.register_clkin(plls_clk50, 50e6)
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pll_idelay.create_clkout(self.cd_idelay, 200e6)
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@ -65,7 +65,7 @@ class _CRG(Module):
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# Video PLL.
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if with_video_pll:
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self.submodules.video_pll = video_pll = S7MMCM(speedgrade=-2)
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self.submodules.video_pll = video_pll = S7MMCM(speedgrade=speed_grade)
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self.comb += video_pll.reset.eq(~plls_reset | self.rst)
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video_pll.register_clkin(plls_clk50, 50e6)
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video_pll.create_clkout(self.cd_hdmi, pix_clk)
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@ -74,10 +74,11 @@ class _CRG(Module):
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False,
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def __init__(self, sys_clk_freq=int(100e6), board_version=1, speed_grade=-2,
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with_ethernet=False, with_etherbone=False,
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eth_ip="192.168.1.50", with_led_chaser=True, with_video_terminal=False,
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with_video_framebuffer=False, video_timing="640x480@60Hz", **kwargs):
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platform = qmtech_wukong.Platform()
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platform = qmtech_wukong.Platform(board_version=board_version,speed_grade=speed_grade)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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@ -87,7 +88,8 @@ class BaseSoC(SoCCore):
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# CRG --------------------------------------------------------------------------------------
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with_video_pll = (with_video_terminal or with_video_framebuffer)
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self.submodules.crg = _CRG(platform, sys_clk_freq, with_video_pll=with_video_pll, pix_clk = video_timings[video_timing]["pix_clk"])
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self.submodules.crg = _CRG(platform, speed_grade, sys_clk_freq, with_video_pll=with_video_pll,
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pix_clk = video_timings[video_timing]["pix_clk"])
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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@ -118,7 +120,7 @@ class BaseSoC(SoCCore):
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Video ------------------------------------------------------------------------------------
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# Video ----------------------------------- -------------------------------------------------
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if with_video_terminal or with_video_framebuffer:
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self.submodules.videophy = VideoS7HDMIPHY(platform.request("hdmi_out"), clock_domain="hdmi")
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if with_video_terminal:
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@ -132,6 +134,8 @@ def main():
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)")
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parser.add_argument("--board-version", default=1, help="Board version 1 or 2 (default: 1)")
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parser.add_argument("--speed-grade", default=-1, help="FPGA speed grade: -1 or -2 (default: -1)")
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ethopts = parser.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
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@ -147,8 +151,14 @@ def main():
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vivado_build_args(parser)
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args = parser.parse_args()
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speed_grade = int(args.speed_grade)
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if speed_grade not in [-1,-2]:
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raise ValueError("Speed grade {} unsupported".format(speed_grade))
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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board_version = int(args.board_version),
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speed_grade = speed_grade,
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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eth_ip = args.eth_ip,
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@ -160,6 +170,7 @@ def main():
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soc.platform.add_extension(qmtech_wukong._sdcard_pmod_io)
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soc.add_spi_sdcard()
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if args.with_sdcard:
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if int(args.board_version) < 2:
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soc.platform.add_extension(qmtech_wukong._sdcard_pmod_io)
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soc.add_sdcard()
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