ti60_f225_dev_kit: Add debug on ethernet.
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@ -77,10 +77,11 @@ class BaseSoC(SoCCore):
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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platform.add_extension(efinix_titanium_ti60_f225_dev_kit.rgmii_ethernet_qse_ios("P1"))
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pads = platform.request("eth", eth_phy)
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self.submodules.ethphy = LiteEthPHYRGMII(
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platform = platform,
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clock_pads = platform.request("eth_clocks", eth_phy),
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pads = platform.request("eth", eth_phy),
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pads = pads,
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with_hw_init_reset = False)
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if with_ethernet:
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self.add_ethernet(phy=self.ethphy, software_debug=True)
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@ -91,9 +92,27 @@ class BaseSoC(SoCCore):
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platform.toolchain.excluded_ios.append(platform.lookup_request("eth_clocks").tx)
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platform.toolchain.excluded_ios.append(platform.lookup_request("eth_clocks").rx)
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platform.toolchain.excluded_ios.append(platform.lookup_request("eth").tx_data)
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platform.toolchain.excluded_ios.append(platform.lookup_request("eth").tx_ctl)
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platform.toolchain.excluded_ios.append(platform.lookup_request("eth").rx_data)
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platform.toolchain.excluded_ios.append(platform.lookup_request("eth").mdio)
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# Extension board on P2 + External Logic Analyzer.
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_pmod_ios = [
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("debug", 0, Pins(
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"L11", # GPIOR_P_15
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"K11", # GPIOR_N_15
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"N10", # GPIOR_P_12
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"M10", # GPIOR_N_12
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),
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IOStandard("1.8_V_LVCMOS")
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),
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]
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platform.add_extension(_pmod_ios)
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debug = platform.request("debug")
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self.comb += debug[0].eq(self.ethphy.tx.sink.valid)
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self.comb += debug[1].eq(self.ethphy.tx.sink.data[0])
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self.comb += debug[2].eq(self.ethphy.tx.sink.data[1])
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# Build --------------------------------------------------------------------------------------------
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def main():
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